Introduction to Microcontrollers Unit 1

MIT-WPU School of Electronics and Communication Engineering S.Y. B. Tech (SEM- IV) Microcontroller and Applications ECE2003B Course Content 1. Introduction to Microcontroller 2. CIP-51 Architecture 3. Peripheral Interfacing and Programming...

MIT-WPU School of Electronics and Communication Engineering S.Y. B. Tech (SEM- IV) Microcontroller and Applications ECE2003B Course Content 1. Introduction to Microcontroller 2. CIP-51 Architecture 3. Peripheral Interfacing and Programming-I 4. Peripheral Interfacing and Programming-II Course Objectives & Course Outcomes: Pre-requisites: Exposure to Digital Electronics Course Objectives: 1. Knowledge: Basics of Microprocessor and Microcontroller architecture and features Integrated Development Environment (IDE) for developing microprocessor and microcontroller-based applications. Interfacing of a microcontroller with various peripherals. 2. Skills: To write assembly language and embedded C programs. To apply knowledge for the development of multidisciplinary projects. 3.Attitude: To select the appropriate microcontroller for the desired application. To develop real-world applications using a microcontroller. Course Objectives & Course Outcomes: Course Outcomes: After completion of this course students will be able to 1. Explain the architecture of the microcontroller (CL-II) 2. Make use of Integrated Development Environment (IDE) for programming and debugging. (CL-III) 3. Apply knowledge of microcontroller interfacing with various peripherals for developing real-world applications. (CL-III) 4. Compare various microcontrollers and select the appropriate microcontroller for the desired application. (CL-IV) Syllabus: Unit 1 Introduction to Microcontroller: Microprocessor and Microcontroller comparison, Microcontroller architecture comparison, Role of microcontroller in Embedded System, Introduction to CIP-51 architecture and block diagram,, Instruction set, and Assembly language programming. Unit 2 CIP-51 Architecture: Reset sources, Oscillator options, Memory Organization, Port structure, Timers, Timer programming, Interrupt handler, Power management modes. (All programs in Embedded C). Unit 3 Peripheral Interfacing and Programming-I: Interfacing of LED, Relay, Buzzer, Switch, 7-segment display, LCD, Keypad, Stepper Motor, DAC ADC programming, Programmable Counter Array (PCA), DC motor control using PWM (All programs in Embedded C). Unit 4 Peripheral Interfacing and Programming-II: Basics of Serial Communication protocol:UART, study of RS 232,RS 485, I2C, and SPI (All programs in Embedded C), Comparative study of various emerging microcontrollers, Microcontroller application Case Study. List of Experiments: Laboratory Exercises / Practical: 1. Simple assembly language programming. 2. Complex assembly language programming. 3. Interfacing LED, Relay, Buzzer, and switch with C8051F340. 4. Interfacing LCD with C8051F340. 5. Interfacing DAC with C8051F340. 6. Interfacing ADC with C8051F340. 7. Interfacing DC motor and control its speed using PWM with C8051F340. 8. Interfacing UART with C8051F340. 9. Interfacing Stepper Motor with C8051F340. 10.Interfacing EEPROM using SPI with C8051F340. 11.Design and implement a microcontroller-based project.  UNIT-I Introduction to Microcontroller Contents Microprocessor and Microcontroller comparison, Microprocessors and microcontroller architecture comparison Role of microcontroller in Embedded System Introduction to CIP-51 architecture and block diagram Memory organization Instruction set Assembly programming Terminologies: Integrated Circuit (IC): A miniaturized electronic circuit that consists of semiconductor devices and passive components contained in a package Central Processing Unit (CPU): This refers to the core of the MCU that executes code Microcontroller Unit (MCU): This is the standard acronym used for microcontrollers, and refers to the full IC that contains the CPU and peripherals. “n-bit” – the “n” refers to the data bus width of the CPU, and is the maximum width of data it can handle at a time Examples: 8-bit MCU, 32-bit MCU Micro-processors and Microcontrollers Microprocessor: General-purpose CPU/ General-purpose Processor (GPP) Emphasis is on flexibility and performance Generic user-interface such as keyboard, mouse, etc. Used in a PC, PDA, cell phone, etc. Microcontroller: Microprocessor + Memory on a single chip Emphasis is on size and cost reduction The user interface is tailored to the application, such as the buttons on a TV remote control Used in a digital watch, TV remote control, car and many common day-to-day appliances Microprocessor Vs Microcontroller  Microprocessor Microcontroller 1 It is only a processor, so memory and Micro Controller has a processor along with I/O components need to be connected internal memory and I/O components and externally and having higher power having lower power consumption(General purpose Consumption (Application specific) Processor) 2. Memory and I/O has to be connected Memory and I/O are already present, and the externally, so the circuit becomes large. internal circuit is small. (A single chip and (Bulkier and Expensive) cost effective) 3. Microprocessors are based on Von Micro controllers are based on Harvard Neumann model architecture 4 High Processing Power in terms of instruction Low processing Power in terms of instruction execution(MIPS) execution(MIPS) 5 CPU word size can be 16/ 32/64 bit CPU word size can be 8/16/32 bit 6 It has no RAM, ROM, Input-Output units, It has a CPU along with RAM, ROM, and other timers, and other peripherals on the peripherals embedded on a single chip. chip. 7 Only word/ byte transferable Also bit transferable 8 More power consumption Less power consumption 9 Examples: Intel 8085, 8086, Motorola’s LPC 2148, C8051F340, MSP430, LPC 1768, STM https://raspberrytips.com/is-raspberry-pi-a-  Role of microcontroller in Embedded System A combination of hardware and software designed to perform a dedicated function Embedded systems are computing systems with tightly coupled hardware and software integration. Designed to perform dedicated function Embedded systems are part of a larger system or product, -e.g., antilock braking system in a car Embedded systems are tightly coupled to their environment 🡪 imposes real- time constraints by the need to interact with the environment https://raspberrytips.com/is-raspberry-pi-a- microcontroller/ Embedded Products Using Microcontrollers (Applications) Home Appliances, intercom, telephones, security systems, garage door openers, answering machines, fax machines, home computers, TVs, cable TV tuner, VCR, camcorder, remote controls, video games, cellular phones, musical instruments, sewing machines, lighting control, paging, camera, pinball machines, toys, exercise equipment Office Telephones, computers, security systems, fax machines, microwave, copier, laser printer, color printer, paging Auto Trip computer, engine control, air bag, instrumentation, security system, transmission control, entertainment, climate control, cellular phone, keyless entry Is 8-bit Still Relevant? “n-bit” – the “n” refers to the data bus width of the CPU, and is the maximum width of data it can handle at a time 8-bit microcontrollers are sufficient and cost-effective for many embedded applications More and more advanced features and peripherals are added to 8-bit processors by various vendors 8-bit MCUs are well-suited for low-power applications that use batteries The 8051 Microcontroller—A Brief History In 1980, Intel introduced the 8051 First device in the MCS-51® family of 8-bit microcontrollers In addition to Intel there are other second source suppliers of the ICs, who make microcontrollers that are compatible with the 8051 architecture. In recent years some companies have incorporated many different and additional features into 8051 In 2000, Silicon Laboratories introduced CIP-51 microcontroller chip (C8051F340) based on the 8051 core CPU https://www.manualslib.com/manual/152880/Silicon-Laboratories- C8051f341.html?page=73#manual https://cselectricalandelectronics.com/different- types-of-microcontrollers-used-in-embedded- system/ Important Basics Microcontroller (Small sized Computer) Differences between Von Neumann and Harvard architecture Comparison of Von Neumann and Harvard Von Neumann architecture Harvard architecture – Fetches instructions and – Fetches Instruction and Data data from a single from two separate memory memory space spaces – Limits operating bandwidth – Improved operating bandwidth – Allows for fixed bus widths – Allows for different bus widths – Architecture --- CISC – Architecture --- RISC – Variable instruction format – Fixed instruction format Control Unit(Hardwired v/s Micro- programmed Control Unit ) To execute an instruction, there are two types of control units Hardwired Control unit and Micro-programmed control unit. 1.Hardwired control units are generally faster than microprogrammed designs. In hardwired control, all the control signals required inside the CPU can be generated using a state counter and a PLA circuit. 2.A microprogrammed control unit is a relatively simple logic circuit that is capable of sequencing through microinstructions and generating control signals to execute each microinstruction.  Concept of Pipeline for Instruction Excecution Fetch Decode Execute RISC (Reduced Instruction Set Computer): The RISC processors have a comparatively smaller set of instructions along with few addressing nodes. The fundamental goal of RISC is to make hardware simpler by employing an instruction set that consists of only a few basic steps used for evaluating, loading, and storing operations. A load command loads data but a store command stores data. CISC (Complex Instruction Set Computer): The CISC processors consist of a larger set of instructions along with multiple addressing nodes. The fundamental goal of CISC is that a single instruction will handle all evaluating, loading, and storing operations. Both CISC and RISC approaches primarily try to increase the performance of a CPU. Here is how both of these work: 1. CISC: This kind of approach tries to minimize the total number of instructions per program, and it does so at the cost of increasing the total number of cycles per instruction. 2. RISC: It reduces the cycles per instruction and does so at the cost of the total number of instructions per program. RISC Vs CISC Sr. : No. Properties RISC (Reduced Instruction CISC (Complex Instruction Set Computer) Set Computer) 1 No. of Instructions Less More 2 Addressing Modes Less More 3 Instruction Formats Less More 4 Instruction Size Fixed Variable 5 Control Unit Hardwired Micro-programmed 6 No. of Bus Cycles to Single CPU cycle (for 80% Multiple CPU cycles execute an instruction Instructions) 7 Control Logic & Simple Complex Decoding Subsystem 8 Pipelining Huge no. of stages of Difficulty in efficient Pipelining implementation 9 Design time & Smaller time & less probable Long time & Significant Probability of Design probability Errors 10 Complexity of Compiler Simpler More complex 11 HLL(High level Supported Not supported language) Instructions * A pipeline is the mechanism a RISC processor uses to execute instructions. Using a pipeline speeds up execution by fetching the next instruction while other instructions are being decoded and executed.  RISC vs. CISC Architecture CISC RISC 1. Complex Instruction taking multiple 1.Simple Instruction taking 1 cycle cycles 2.Only LOADs, STOREs access 2. Any Instruction may access memory memory 3. Designed around Instruction Set 3.Designed around pipeline 4. Instruction interpreted by micro 4.Instruction executed by h/w program 5.Fixed format Instruction 5. Variable format Instruction 6.Few Instruction and modes 6. Many Instruction and modes 7.Complexity in the compiler 7. Complexity in the micro program 8.Multiple register sets 8. Single register set Thin quad flat pack (TQFP) Introduction to CIP-51 Core (1st Unit is focused on CIP -51 Core) Block Diagram C8051F340 Memory Organization of C8051F340 (Will be referred again in unit 2) 64 KB ROM for writing code 256 bytes data memory space Additional storage of 4kB Program counter (PC) is register which contains current location(Address) of code execution in code memory. Micro Controller performs all operations in hex 1. First 32 bytes of memory location in RAM are used as registers.(R0 to R7) 2. Register banks are selected by RS1 and RS0 bits in the program status word  Instruction Set and Assembly Programming An instruction is made up of an operation code (op-code) followed by either zero, one or two bytes of operands The op-code identifies the type of operation to be performed while the operands identify the source and destination of the data. [Label:] Instructions The operand can be: [//Comments] The data value itself A CPU register A memory location An I/O port An assembly language instruction has four fields: [Label:] mnemonic [operands] [;comments] Ex: MOV A, #00H ;put 0 in the accumulator A = 00000000 Instructions Format Assembly language instructions specify the program code that is to be assembled by the Ax51 assembler. The Ax51 assembler translates the assembly instructions in your program into machine code and stores the resulting code in an object file. Assembly instructions have the following general format: label: mnemonic operand , operand /, operand ; comment label symbol name that is assigned the address at which the instruction is located. is the ASCII text string that symbolically represents a machine mnemonic language instruction. operand is an argument that is required by the specified mnemonic. is an optional description or explanation of the instruction. A comment may comment contain any text you wish. Comments are ignored by the assembler.  Using Operands and Expressions Assembler instructions support a wider variety of operands than do directives. Some instructions require no operands and some may require up to 3 operands. Multiple operands are separated by commas. For example: MOV R2, #0 The number of operands that are required and their types depend on the instruction or directive that is specified. In the following table, the first four operands can also be expressions. Instruction operands can be classified as one the following types: Addressing Modes Five modes of addressing The different addressing modes determine how the operand byte is selected Description Addressing Modes Instruction Operand is in register Register MOV A, B Operand is in memory Direct MOV 30H,A location(register to memory location transfer Indirect ADD A,@R0 Operand address is in the register Immediate ADD A,#80H Operand is specified in the instruction itself Indexed MOVC A,@A+PC Operand is at address specified by register+address pointer Important Registers for programming in Assembly Different Versions of MOV Instruction Different Versions of MOV Instruction Different Versions of ADD Instruction Mnemon ics Assembler Directives and Data Type Assembler Directives ORG EQU END Data Type: DB Note: For the mnemonic, number of bytes, and number of clock cycles for each instruction refer Table 9.1 in the datasheet Many instructions have required arguments that are described in the following table: Argument Description Addr11 An 11-bit address destination. This argument is used by ACALL and AJMP (11 bit instructions. The target of the CALL or JMP must lie within the same 2K page as the address) first byte of the following instruction. Addr16 (16 bit A 16-bit address destination. This argument is used by LCALL and LJMP instructions. address) bit A direct addressed bit in internal data RAM or SFR memory. direct An internal data RAM location (0-127) or SFR (128-255). immediate A constant included in the instruction encoding. A signed (two's complement) 8-bit offset (-128 to 127) relative to the first byte of the offset following instruction. @Ri An internal data RAM location (0-255) addressed indirectly through R0 or R1. Rn Register R0-R7. Arithmetic Flags Flag: It is a 1-bit register that indicates the status of the result from an operation Flags are either at a flag-state of value 0 or 1 Arithmetic flags indicate the status of the results from mathematical operations ( +, −, *, / ) There are 4 arithmetic flags in the 8051 Carry (C) Auxiliary Carry (AC) Overflow (OV) Parity (P) Program Status Word (PSW)or Flag Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CY AC FO RS1 RS0 OV UD P Symbol Function CY Carry flag AC Auxiliary Carry flag (For BCD Operations) F0 Flag 0 (Available to the user for General Purpose) RS1, Register bank select: RS0 RS1 RS0 Working Register Bank and Address 0 0 Bank0 0 1 Bank1 1 0 Bank2 (D:0x10 - D:0x17) 1 1 Bank3 (D:0x18H - D:0x1F) 0V Overflow flag UD User definable flag P Parity flag; P=1 for Odd no. of 1’s; P=0 for Even no. of 1’s Related Terms https://developer.arm.com/documentation/101655/0961/8051-Instruction-Set-Manual/ Instructions/MOV?lang=en MOV instruction Documentation C8051F340 Instruction set  MOV dest, source Sr. No Mnemonic Description Data Transfer Instruction 1 MOV A, Rn Move register to accumulator 2 MOV A, direct Move direct byte to accumulator 3 MOV A, @ Ri Move indirect RAM to accumulator 4 MOV A, #data Move immediate data to accumulator 5 MOV Rn, A Move accumulator to register 6 MOV Rn, direct Move direct byte to register 7 MOV Rn, #data Move immediate data to register 8 MOV direct, A Move accumulator to direct byte 9 MOV direct, Rn Move register to direct byte 10 MOV direct, direct Move direct byte to direct 11 MOV direct, @Ri Move indirect RAM to direct byte 12 MOV direct, #data Move immediate data to direct byte 13 MOV @Ri, A Move accumulator to indirect RAM 14 MOV @Ri, direct Move direct byte to indirect RAM 15 MOV @Ri, #data Move immediate data to indirect RAM Data Transfer Instructions 16 MOV DPTR, #data 16 Load data pointer with a 16-bit constant 17 MOVC A, @A+DPTR Move code byte relative to DPTR to accumulator 18 MOVC A,@A+PC Move code byte relative to PC to accumulator 19 MOVX A, @Ri Move external RAM (8-bit addr) to accumulator 20 MOVX A, @DPTR Move external RAM (16-bit addr) to accumulator 21 MOVX @Ri, A Move accumulator to external RAM (8-bit addr) 22 MOVX @DPTR,A Move accumulator to external RAM (16-bit addr) 23 PUSH direct Push direct byte onto stack 24 POP direct Pop direct byte from stack 25 XCH A, Rn Exchange register byte with accumulator 26 XCH a, direct Exchange direct byte with accumulator 27 XCH A, @Ri Exchange indirect RAM with accumulator 28 XCHD A, @Ri Exchange low order digit indirect RAM with accumulator Arithmetic Instructions Sr. No Mnemonic Description 29 ADD A, Rn Add register to accumulator 30 ADD A, Direct Add direct byte to accumulator 31 ADD A, @ Ri Add indirect RAM to accumulator 32 ADD A, #data Add immediate data to accumulator 33 ADDC A, Rn Add register to accumulator with carry 34 ADDC A, direct Add direct byte to accumulator with carry 35 ADDC A, @Ri Add indirect RAM to accumulator with carry 36 ADDC A, #data Add immediate data to accumulator with carry 37 SUBB A, Rn Subtract register from accumulator with borrow 38 SUBB A, Direct Subtract direct byte from accumulator with borrow 39 SUBB A, @Ri Subtract indirect RAM from accumulator with borrow 40 SUBB A, #data Subtract immediate data from accumulator with borrow Arithmetic Instructions 41 INC A Increment Accumulator 42 INC Rn Increment register 43 INC direct Increment direct byte 44 INC @Ri Increment indirect RAM 45 DEC A Decrement accumulator 46 DEC Rn Decrement register 47 DEC direct Decrement direct RAM 48 DEC @Ri Decrement indirect RAM 49 INC DPTR Increment data pointer 50 MUL AB Multiply A and B 51 DIV AB Divide A by B 52 DA A Decimal adjust accumulator Logical Instructions Sr. Mnemonic Description No 53 ANL A, Rn AND register to accumulator 54 ANL A, Direct AND direct byte to accumulator 55 ANL A, @ Ri AND indirect RAM to accumulator 56 ANL A, #data AND immediate data to accumulator 57 ANL direct, A AND accumulator to direct byte 58 ANL direct, #data AND immediate data to direct byte 59 ORL A, Rn OR register to accumulator 60 ORL A, direct OR direct byte to accumulator 61 ORL A, @Ri OR indirect RAM to accumulator 62 ORL A, #Data OR immediate data to accumulator 63 ORL direct, A OR accumulator to direct byte Logical Instructions 64 ORL direct, #data OR immediate data to direct byte 65 XRL A, Rn EX-OR register to accumulator 66 XRL A, direct EX-OR direct byte to accumulator 67 XRL A, @Ri EX-OR indirect RAM to accumulator 68 XRL A, #Data EX-OR immediate data to accumulator 69 XRL direct, A EX-OR accumulator to direct byte 70 XRL direct, #data EX-OR immediate data to direct byte 71 CLR A Clear Accumulator 72 CPL A Complement Accumulator 73 RL A Rotate accumulator left 74 RLC A Rotate accumulator left through carry 75 RR A Rotate accumulator right 76 RRC A Rotate accumulator right through carry 77 SWAP A Swap nibbles within the accumulator Boolean Variable Manipulation Instructions Sr. No Mnemonic Description 78 CLR C Clear Carry 79 CLR bit Clear direct bit 80 SETB C Set Carry 81 SETB bit Set direct bit 82 CPL C Complement carry 83 CPL bit Complement direct bit 84 ANL C, bit AND direct bit to carry 85 ANL C, /bit AND complement of direct bit to carry 86 ORL C, bit OR direct bit to carry 87 ORL C, /bit OR complement of direct bit to carry 88 MOV C, bit Move direct bit to carry 89 MOV bit, C Move carry to direct bit 90 JC rel Jump if carry is set 91 JNC rel Jump if carry not set 92 JB bit, rel Jump if direct bit is set 93 JNB bit, rel Jump is direct bit is not set 94 JBC bit, rel Jump if direct bit is set and clear bit Instructions that affect PSW X can be 0 or 1 Program Branching Instructions Sr. No Mnemonic Description 95 ACALL addr11 Absolute subroutine call 96 LCALL addr16 Long subroutine call 97 RET Return from subroutine 98 RETI Return from interrupt 99 AJMP addr11 Absolute Jump 100 LJMP addr16 Long Jump 101 SJMP rel Short Jump (relative addr) 102 JMP @A+DPTR Jump indirect relative to DPTR 103 JZ rel Jump is accumulator is zero 104 JNZ rel Jump if accumulator is not zero 105 CJNE A, direct, rel Compare direct byte to accumulator and jump if not equal 106 CJNE A, #data, rel Compare immediate to accumulator and jump if not equal 107 CJNE Rn, #data, rel Compare immediate to register and jump if not equal 108 CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal 109 DJNZ Rn, rel Decrement register and jump if not zero 110 DJNZ direct, rel Decrement direct byte and jump if not zero 111 NOP No operation The flag bits affected by the ADD instruction are CY, P, AC, and OV Assembly Programs ▪Addition of n 8-bit numbers ▪Addition of BCD numbers ▪Addition of two 16-bit numbers ▪Find square of a number using DPTR ▪Program to count number of Odd and Even numbers from a given array ▪Program to count number if Positive and Negative numbers from a given array MOV/MOVC/MOVX Instructions MOV The MOV instruction moves data bytes between the two specified operands. The byte specified by the second operand is copied to the location specified by the first operand. The source data byte is not affected. MOV A, #0FFh MOV A, R6 MOVC The MOVC instruction moves a byte from the code or program memory to the accumulator MOV A, @A+PC MOVX The MOVX instruction transfers data between the accumulator and external data memory. External memory may be addressed via 16-bits in the DPTR register or via 8-bits in the R0 or R1 registers. When using 8-bit addressing, Port 2 must contain the high-order byte of the address. MOVX A, @R1 MOVX A, @DPTR Program 1:Addition of two 16bit Numbers Algorithm Consider first 16 bit operand:AB20H Consider second 16 bit operand :65DE Result must be stored such that : MSB Byte in R0 : LSB Byte in R1 Carry Reflected in carry flag Result of Addition is 110FE Carry  Some instructions related to carry Flag ADDC The ADDC instruction adds a byte value and the value of the carry flag to the accumulator. The results of the addition are stored back in the accumulator. Several of the flag registers are affected. Example: ADDC A, #23h CLR The CLR instruction sets the specified destination operand to a value of 0. Example: CLR C SETB The SETB instruction sets the bit operand to a value of 1. This instruction can operate on the carry flag or any other directly addressable bit. No flags are affected by this instruction. Example: SETB C Program1: Addition of two 16 bit Numbers ORG 0000H ; Operand 1 (AB20H) Operand 2 (65DE) CLR C ;MAKE CY=0 MOV A,#020H ;LOWER BYTE OF OPERAND 1(20H) IN A ADD A,#0DEH ;ADD LOWER BYTE OF OPERAND (DE)2 WITH A MOV R1,A ;STORE Lower byte OF RESULT IN R1 MOV A,#65H ;HIGHER BYTE OF OPERAND 2 IN A ADDC A,#0ABH ; ADD WITH HIGHER BYTE OF OPERAND 1 MOV R0,A ;STORES MSB OF RESULT IN R0 END Increment /Decrement INC The INC instruction increments the specified operand by 1. An original value of 0FFh or 0FFFFh overflows to 00h or 0000h. No flags are affected by this instruction. Example: INC A(A=A+1) register content increment INC 34h Address increment INC DPTR INC Rn Logical: OR, XOR, AND, SWAP MOV A, #20H //0010 0000// MOV R0, #03H //0000 0011// XRL A, R0 // 0010 0011// What will be the content in A ? MOV A, #20H //0010 0000// MOV R0, #03H //0000 0011// SWAP A // A= 02H // Addition of 5, 8 bit numbers Use memory location 0x40 to 0x44 for storing numbers Address location 45 and 46 is used for storing result Address pointer is set in R0 N bit value is set in R2(5 in our case)(Count Register) Set result location and accumulator to 0 Add first number at location 0X40 with accumulator If carry is generated increment value at address 0x45H If no carry increment address pointer in R0, and decrement count register Go on decrementing R2 till it becomes zero. Store the result in accumulator at memory location 0x46H Jump Instructions(Unconditional) JMP The JMP instruction transfers execution to the address generated by adding the 8-bit value in the accumulator to the 16-bit value in the DPTR register. Neither the accumulator nor the DPTR register are altered. No flags are affected by this instruction. JMP @A+DPTR AJMP LABEL The destination address must be located in the same 2KByte block of program memory as the opcode following the AJMP instruction. No flags are affected. LJMP The LJMP instruction transfers program execution to the specified 16-bit address. Jump Instructions(Unconditional)… SJMP The SJMP instruction transfers execution to the specified address. The address is calculated by adding the signed relative offset in the second byte of the instruction to the address of the following instruction. The range of destination addresses is from 128 before the next instruction to 127 bytes after the next instruction. SJMP Label Conditional branching or jump instructions JC The JC instruction branches to the specified address if the carry flag is set. Otherwise, execution continues with the next instruction. No flags are affected by this instruction. JC LABEL JB The JB instruction branches to the address specified in the second operand if the value of the bit specified in the first operand is 1. The bit that is tested is not modified. No flags are affected by this instruction. JB bit, offset JB P1.2 LABEL Conditional branching or jump instructions CJNE The CJNE instruction compares the first two operands and branches to the specified destination if their values are not equal. If the values are the same, execution continues with the next instruction. CJNE A, #01H, LABEL DJNZ The DJNZ instruction decrements the byte indicated by the first operand and, if the resulting value is not zero, branches to the address specified in the second operand. Addition of 5(N), 8 bit numbers stored in memory Memory Location Data Values ORG 0000H 40H 01H MOV R0, #40H 41H 02H MOV R2, #05H MOV 46H,#00H 42H 03H MOV 45H,#00H 43H 04H MOV A,#00H LABEL2:ADD A,@R0 44H 05H LABEL1:INC R0 45H 00H(MSB of result) DJNZ R2, LABEL2 46H 00H(LSB of result) MOV 46H,A END Special Insructions DA The DA instruction adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition. If Accumulator bits 3-0 are greater than nine (xxx1010-xxx1111), or if the AC flag is one, six is added to the Accumulator, producing the proper BCD digit in the low-order nibble. This internal addition would set the carry flag if a carry-out of the low-order four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise. If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxx-111xxxx), these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but would not clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple precision decimal addition. OV is not affected. All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal conversion by adding 00H, 06H, 60H, or 66H to the Accumulator, depending on initial Accumulator and PSW conditions. Find square of a number using DPTR ORG 0000H MOV DPTR, #300H ; load look-up table address BACK: MOV A, #09 ; get X MOVC A, @A+DPTR ; get X square from table MOV 40H , A SJMP BACK ; keep doing it ORG 300H TABLE: DB 0, 1, 4, 9, 16, 25, 36, 49, 64, 81 END Finding Square of Number 1.Initialize R0 with memory address where all squares are stored and R1 with 0. 2.Increment R1 to find the square of a number. 3.Find the square of a number by multiplying A and B with same number. 4.Store the result with the assigned address array. ORG 0000h LJMP MAIN ORG 40h MAIN: MOV R0,#10H ; memory address where all the squares will be stored MOV R1,#00 LOOP: INC R1 ;incrementing each time to generate a new square MOV A,R1 MOV B,R1 MUL AB ;finding the square of a number MOV @R0,A ;storing the square of all the numbers in an array INC R0 CJNE R1,#10,LOOP ; checking the counter value whether it has reached zero END Rotate Instructions RL The RL instruction rotates the eight bits in the accumulator left one bit position. Bit 7 of the accumulator is rotated into bit 0, bit 0 into bit 1, bit 1 into bit 2, and so on. No flags are affected by this instruction. Example RL A RR The RR instruction rotates the eight bits in the accumulator right one bit position. Bit 0 of the accumulator is rotated into bit 7, bit 7 into bit 6, and so on. No flags are affected by this instruction. Example RR A  MOV A, #25h Rotate RR A Instructio ns What will be the content in A ? MIT-WPU ECE Program to count number of 1’s in a given byte describes RRC Instruction MOV R1, #00H ; Register to store count MOV R2, #08H ; Loop variable MOV A, #0FF ; Take any number here its 0x FF back: RRC A ; Rotate right through carry flag JC count ; If carry is 1 increment counter SJMP next ; go to next counting count: INC R1 ; counting number of ones in memory Next: DJNZ R2, back; Continue to count till all bits are checked END Program to count number of Odd and Even numbers from a given array(Describes DIV AB) ORG 0000H MOV R2, #00H Uses DIV AB instruction: Divides accumulator MOV R3, #00H with B register MOV R0, #40H MOV R4,#05 The resulting quotient is placed in the back: accumulator. Remainder MOV A, @ R0; take the first number in acc MOV B , #02H; immediate value 2 in reg B Is placed in B register. If remainder is 1 then DIV AB; divide A by B number is odd. INC R0 MOV R1, B, Shift remainder in R1 CJNE R1, #00H, odd, if R1 is not zero number is odd SJMP even; otherwise number is even Odd: INC R2 ;R2 for odd DJNZ R4, back Even: INC R3 ;R3 for Even DJNZ R4, back ;check this for all 5 nos stored in memory END  Program to find positive and negative numbers(Describes RLC and use of carry flag) A negative number has its MSB as binary 1. Hence rotate the number through carry to the left and then decide upon status of carry flag ORG 0000H ; Origin MOV A,#08h ; move immediate number RLC A ; Rotate accumulator left through carry JC Negative ; If carry present number is negative move to label negative Negative: MOV A, #01H ; moving 0 to acc show number is positive Positive: MOV A, #00h ; Moving 0 to acc to show number is Positive END  Addition of 8 bit 2 digit BCD(Describes use of call and RET use of equate directive, DA A) ; R5=R1+R2 ORG 000H BCD_1 EQU 20H BCD_2 EQU 90H MAIN: MOV R1, #BCD_1 MOV R2, #BCD_2 LCALL BCDADD SJMP MAIN BCDADD:MOV A,R1 ADD A,R2 DA A MOV R5, A RET END References https://www.silabs.com/documents/public/datasheets/C8051F34x.pdf Muhammas Mazidi, Janice Mazidi and Rolin McKinlay, “ The 8051 Microcontroller and Embedded Systems using Assembly and C”, Pearson Education, 2nd edition Instruction set http://www.keil.com/support/man/docs/is51/is51_xch.htm