embedded systems.pdf

Embedded System 06-08-2024 Parul Mathur 1 Syllabus Unit 1 ARM Cortex M3 Processor: Overview of the Cortex-M3 - Registers – Special Registers -Operation Modes - Built-In Nested Vectored Interrupt Controller - Memory Map – Bus Interfaces - Instruction Set - Memory Systems- Co...

Embedded System 06-08-2024 Parul Mathur 1 Syllabus Unit 1 ARM Cortex M3 Processor: Overview of the Cortex-M3 - Registers – Special Registers -Operation Modes - Built-In Nested Vectored Interrupt Controller - Memory Map – Bus Interfaces - Instruction Set - Memory Systems- Cortex-M3 Implementation Overview – Exceptions - Nested Vectored Interrupt Controller and Interrupt Control - Interrupt Behavior - Cortex-M3 Programming - Advanced Programming Features and System Behavior - The Memory Protection Unit - Other Cortex-M3 Features - Debug Architecture - Debugging Components. Unit 2 MSP432 Architecture and Peripherals - Introduction to MSP432 Architecture – Memory Map – Clock System – Power Control Manager – Power Mode – DMA – Digital Input Output – Enhanced Universal Serial Communication Interface – Precision ADC – Programming MSP432 using Energia IDE. Unit 3 Introduction to FreeRTOS and Programming - Introduction to RTOS – Task States – Semaphores – Scheduling – Preemptive - Rate Monotonic – Earliest Deadline First - Inter Task Communication – Message Queue – MailBox – Pipes – Introduction to FreeRTOS – Task Management – Interrupt Management – Queue Management. Text Book(s) Joseph Yiu, “The Definitive Guide to the ARM Cortex M3”, Second Edition, Elsevier Inc., 2010. Muhammad Ali Mazidi, Shujen Chen, Sepehr Naimi, “TI MSP432 ARM Programming for Embedded Systems”, Volume 4, 2016. 06-08-2024 Parul Mathur 2 06-08-2024 Parul Mathur 3 06-08-2024 Parul Mathur 5 06-08-2024 Parul Mathur 6 06-08-2024 Parul Mathur 7 06-08-2024 Parul Mathur 8 06-08-2024 Parul Mathur 9 06-08-2024 Parul Mathur 10 06-08-2024 Parul Mathur 11 06-08-2024 Parul Mathur 12 06-08-2024 Parul Mathur 13 06-08-2024 Parul Mathur 14 06-08-2024 Parul Mathur 15 Based on Performance Requirements Real-Time Embedded Systems Hard Real-Time Systems: Soft Real-Time Systems Stand-Alone Embedded Systems Networked Embedded Systems Mobile Embedded Systems 06-08-2024 Parul Mathur 16  Real-Time Embedded Systems Hard Real-Time Systems: Require strict timing constraints where the system must respond within a specific time limit. Examples include medical devices, automotive airbag systems, and industrial control systems. Soft Real-Time Systems: Timing constraints are less stringent, and occasional delays are acceptable. Examples include multimedia systems and mobile phones. 06-08-2024 Parul Mathur 17  Stand-Alone Embedded Systems Operate independently without needing a host system. Examples include digital watches, calculators, and home appliances like microwaves. Networked Embedded Systems Connected to a network to share data and resources. Examples include smart home devices, network routers, and surveillance systems. Mobile Embedded Systems Portable and designed for mobile use. Examples include smartphones, tablets, and GPS devices. 06-08-2024 Parul Mathur 18 Based on Functionality of Microcontroller 06-08-2024 Parul Mathur 19 06-08-2024 Parul Mathur 20 06-08-2024 Parul Mathur 21 06-08-2024 Parul Mathur 22 06-08-2024 Parul Mathur 23 06-08-2024 Parul Mathur 24 06-08-2024 Parul Mathur 25 06-08-2024 Parul Mathur 26 06-08-2024 Parul Mathur 27 06-08-2024 Parul Mathur 28 06-08-2024 Parul Mathur 29  Key Characteristics of Embedded Systems: ❑ Dedicated Functionality: Embedded systems are designed to perform a specific task or set of tasks. Unlike general- purpose computers, they are optimized for particular functions, making them more efficient and reliable in their designated roles. ❑ Real-Time Operation: Many embedded systems operate in real-time, meaning they must respond to inputs or events within a defined time frame. Real-time performance is crucial for applications like automotive control systems, medical devices, and industrial automation. ❑ Resource Constraints: Embedded systems often have limited resources, such as memory, processing power, and power consumption. These constraints require careful optimization of software and hardware to ensure efficient operation. ❑ Reliability and Stability: Reliability is critical in embedded systems, especially in applications where failure could lead to significant consequences (e.g., medical devices, automotive systems). Embedded systems are designed to run continuously for long periods with minimal maintenance. ❑ Low Power Consumption: Many embedded systems are used in battery-powered devices, making low power consumption a key requirement. Power-efficient designs help extend battery life and reduce energy costs. 06-08-2024 Parul Mathur 30  Key Characteristics of Embedded Systems: ❑ Small Size and Weight: Embedded systems are often designed to be compact and lightweight to fit into the physical constraints of their applications. This is important in portable devices, wearable technology, and space-constrained environments. ❑ Integration with Hardware: Embedded systems are tightly integrated with the hardware they control. This integration allows for efficient communication and control of peripherals such as sensors, actuators, displays, and communication modules. ❑ Firmware: The software running on embedded systems, known as firmware, is typically stored in non-volatile memory (such as ROM, EEPROM, or flash memory). Firmware is designed to be robust and reliable, often running directly on the hardware with minimal abstraction layers. ❑ Specific User Interfaces: Embedded systems may have specialized user interfaces tailored to their function. This could range from simple LED indicators and buttons to complex graphical user interfaces on touchscreen displays. ❑ Networking and Connectivity: Many modern embedded systems are networked, either locally or through the internet (IoT devices). Connectivity features such as Wi-Fi, Bluetooth, Zigbee, or Ethernet enable remote monitoring, control, and data exchange. 06-08-2024 Parul Mathur 31  Key Characteristics of Embedded Systems: ❑ Cost Constraints: Cost efficiency is often a crucial consideration in embedded system design. Balancing performance and functionality with manufacturing costs is essential, especially in high-volume consumer products. ❑ Security: Embedded systems often handle sensitive data or control critical operations, making security a vital aspect. Security measures may include encryption, secure boot, authentication, and protection against physical tampering. 06-08-2024 Parul Mathur 32 06-08-2024 Parul Mathur 33 06-08-2024 Parul Mathur 34 06-08-2024 Parul Mathur 35 06-08-2024 Parul Mathur 36 06-08-2024 Parul Mathur 37 06-08-2024 Parul Mathur 38 06-08-2024 Parul Mathur 39 06-08-2024 Parul Mathur 40 06-08-2024 Parul Mathur 41 06-08-2024 Parul Mathur 42 06-08-2024 Parul Mathur 43 06-08-2024 Parul Mathur 44 06-08-2024 Parul Mathur 45 06-08-2024 Parul Mathur 46 06-08-2024 Parul Mathur 47 06-08-2024 Parul Mathur 48 06-08-2024 Parul Mathur 49 06-08-2024 Parul Mathur 50 06-08-2024 Parul Mathur 51 06-08-2024 Parul Mathur 52 06-08-2024 Parul Mathur 53 06-08-2024 Parul Mathur 54 06-08-2024 Parul Mathur 55 06-08-2024 Parul Mathur 56 06-08-2024 Parul Mathur 57 06-08-2024 Parul Mathur 58 06-08-2024 Parul Mathur 59 06-08-2024 Parul Mathur 60 06-08-2024 Parul Mathur 61  5. Different types of memory ▪ Flash Memory ▪ SRAM (Static Random-Access Memory) ▪ EEPROM (Electrically Erasable Programmable Read-Only Memory) ▪ FRAM (Ferroelectric RAM) FRAM (Ferroelectric RAM) Definition: FRAM (Ferroelectric Random Access Memory) is a type of non-volatile memory that combines the benefits of both RAM and conventional non-volatile memory like Flash. It uses a ferroelectric layer to achieve non-volatility, meaning it retains data without requiring a continuous power supply. 06-08-2024 Parul Mathur 62 06-08-2024 Parul Mathur 63  The primary difference between volatile and non-volatile memory is whether they retain data without power. Volatile memory is faster and used for temporary data storage, whereas non-volatile memory is used for permanent data storage The number of write cycles refers to the number of times data can be written to a memory cell before it starts to degrade or fail. Different types of memory technologies have varying endurance levels, which makes them suitable for different applications. 06-08-2024 Parul Mathur 64 06-08-2024 Parul Mathur 65 06-08-2024 Parul Mathur 66 06-08-2024 Parul Mathur 67 06-08-2024 Parul Mathur 68 06-08-2024 Parul Mathur 69 06-08-2024 Parul Mathur 70 06-08-2024 Parul Mathur 71 06-08-2024 Parul Mathur 72 06-08-2024 Parul Mathur 73 06-08-2024 Parul Mathur 74 06-08-2024 Parul Mathur 75 06-08-2024 Parul Mathur 76.EXE file are used for simulation and debugging 06-08-2024 Parul Mathur 77 06-08-2024 Parul Mathur 78 ❖ Complier convert high level into low level coding 06-08-2024 Parul Mathur 79  in Machine laungauge 06-08-2024 Parul Mathur 80 06-08-2024 Parul Mathur 81 06-08-2024 Parul Mathur 82 06-08-2024 Parul Mathur 83 Can be loaded into memeory 06-08-2024 Parul Mathur 84.EXE file are used for simulation and debugging 06-08-2024 Parul Mathur 85 06-08-2024 Parul Mathur 86 06-08-2024 Parul Mathur 87  Development environment 06-08-2024 Parul Mathur 88 06-08-2024 Parul Mathur 89 06-08-2024 Parul Mathur 90  Energia IDE Download procedure explained in the following link Similar to Ardunio. Need to install few drivers. The procedure is for MSPEXP430G2ET microcontroller https://www.youtube.com/watch?v=vz94tnh1mrg 06-08-2024 Parul Mathur 91 06-08-2024 Parul Mathur 92 06-08-2024 Parul Mathur 93  Blink led 06-08-2024 Parul Mathur 94 06-08-2024 Parul Mathur 95 06-08-2024 Parul Mathur 96 07-08-2024 Parul Mathur 97 06-08-2024 Parul Mathur 98 06-08-2024 Parul Mathur 99 06-08-2024 Parul Mathur 100  Difference between the two IRQ (Interrupt Request), FIQ (Fast Interrupt Request), NMI (Non-Maskable Interrupt), DMIPS stands for Dhrystone MIPS (Million Instructions Per Second), NVIC (Nested Vectored Interrupt Controller), 06-08-2024 Parul Mathur 101  Clock speed CortexM3 ARM7TDMI 06-08-2024 Parul Mathur 102 06-08-2024 Parul Mathur 103 06-08-2024 Parul Mathur 104 06-08-2024 Parul Mathur 105 06-08-2024 Parul Mathur 106 06-08-2024 Parul Mathur 107  Context Switching 06-08-2024 Parul Mathur 108  Context Switching 06-08-2024 Parul Mathur 109 06-08-2024 Parul Mathur 110 06-08-2024 Parul Mathur 111 06-08-2024 Parul Mathur 112 06-08-2024 Parul Mathur 113 06-08-2024 Parul Mathur 114 06-08-2024 Parul Mathur 115 06-08-2024 Parul Mathur 116 06-08-2024 Parul Mathur 117 06-08-2024 Parul Mathur 118  1. Architecture ARM7 and Cortex Architectures ARM7 Architecture: Memory Model: ARM7 processors generally follow the von Neumann architecture. Unified Memory: ARM7 typically uses a unified memory space where both instructions and data reside. Single Bus: Instructions and data are accessed using a single set of address and data buses. Cortex Architecture (including Cortex-M3): Memory Model: Cortex processors, including Cortex-M3, typically follow a modified Harvard architecture. Separate Memory Spaces: Cortex processors often feature separate instruction and data memory spaces, especially in the Cortex-M series. Separate Buses: Different buses are used for instruction fetches and data transfers, enhancing efficiency and performance. 06-08-2024 Parul Mathur 119 06-08-2024 Parul Mathur 120 2. Pipelining Architecture ARM7 Pipeline The ARM7 series processors typically feature a three-stage pipeline: 1.Fetch Stage: 1. The processor fetches the next instruction from memory. 2. The instruction fetch unit prepares the instruction for decoding. 2.Decode Stage: 1. The fetched instruction is decoded to determine the operation and operands. 2. The necessary control signals and register accesses are prepared. 3.Execute Stage: 1. The decoded instruction is executed. 2. Arithmetic or logical operations are performed, memory accesses are made, or control flow changes occur. 3. Results are written back to registers or memory. 06-08-2024 Parul Mathur 121  2. Pipelining Architecture Cortex-M3 Pipeline The Cortex-M3, on the other hand, features a more advanced three- stage pipeline with optional pipeline stages for optimization: 1.Fetch Stage: 1. Similar to ARM7, the Cortex-M3 fetches the next instruction from memory. 2.Decode : 3.Execute Stage ,Memory Access and Writeback Stage: 06-08-2024 Parul Mathur 122 2. Pipelining Architecture 06-08-2024 Parul Mathur 123 06-08-2024 Parul Mathur 124 06-08-2024 Parul Mathur 125 06-08-2024 Parul Mathur 126 06-08-2024 Parul Mathur 127 06-08-2024 Parul Mathur 128 06-08-2024 Parul Mathur 129 06-08-2024 Parul Mathur 130 06-08-2024 Parul Mathur 131  3. Instruction set ARM7 can use arm and thumb two instruction sets, while Cortex only supports the latest Thumb-2 instruction set. The advantage of this design is that it eliminates the switch between thumb and arm code, which can degrade performance for earlier processors. The Thumb-2 instruction set is designed specifically for the C language, and includes the If/then structure (which predicts conditional execution of the next four statements), hardware division, and the status domain operation. The Thumb-2 instruction set allows users to maintain and modify applications at the C code level, and the C code section is very easy to reuse. The Thumb-2 instruction set also includes the ability to invoke assembly code: Luminary Company does not consider it necessary to use any assembly language. Combined with these advantages, the development of new products will be easier to achieve, time-to-market is greatly shortened. 06-08-2024 Parul Mathur 132  3.Instruction set 06-08-2024 Parul Mathur 133 06-08-2024 Parul Mathur 134 ARM7 use ARM and Thumb instruction in switching mode 06-08-2024 Parul Mathur 135  How Thumb2 instruction set works Thumb-2 is an extension to the original Thumb instruction set, introduced to provide a better balance between code density and performance by combining both 16-bit and 32-bit instructions. This allows Thumb-2 to offer the high code density of Thumb with the flexibility and power of ARM's 32-bit instructions. Switching Between 16-bit and 32-bit Instructions ❑The processor automatically decodes the instruction width based on the instruction's format. ❑When the processor fetches an instruction, it checks whether it is a 16- bit or 32-bit instruction and decodes it accordingly. 06-08-2024 Parul Mathur 136  How Thumb2 instruction set works 06-08-2024 Parul Mathur 137  4.Interrupt ❑Another innovation in cortex is the nested vector interrupt controller Nvic (Nested vector Interrupt Controller). ARM7 Utilizes a Vectored Interrupt Controller (VIC) with support for basic interrupt handling and fixed priority levels. ❑In contrast to the external interrupt controller used by the ARM7, the cortex core incorporates an interrupt controller that can be configured by the chip manufacturer to provide a basic 32 physical interrupt with 8 levels of priority, up to 240 physical interrupts and 256 interrupt priority. ❑ This type of design is deterministic and has low latency, and is ideal for automotive applications. 06-08-2024 Parul Mathur 138  4.Interrupt 06-08-2024 Parul Mathur 139  4.Interrupt Nvic is using a stack-based exception model. When processing interrupts, the program counters, program status registers, link registers, and universal registers are pressed into the stack, and after the interrupt processing is complete, the registers are restored. Stack processing is done by hardware and does not require assembly language to create a stack operation for the interrupt service program. An interrupt nesting can be implemented. Interrupts can be changed to use a higher priority than the previous service program, and can change the priority state at run-time. Using the end-of-chain (tail-chaining) continuous interrupt technology consumes only three clock cycles, which significantly reduces latency and improves performance compared to 32 clock cycles of continuous pressure and out stacks. 06-08-2024 Parul Mathur 140  4.Interrupt If the Nvic has already pressed the stack before the higher- priority interrupts arrive, it is only necessary to get a new vector address that can serve the higher-priority interrupts. Similarly, Nvic does not use the stack operation to serve new interrupts. This approach is completely deterministic and has low latency. 06-08-2024 Parul Mathur 141  5.Sleep mode ARM7 Sleep Modes 1.Idle Mode: 1. Description: In Idle mode, the CPU core is halted while peripherals and interrupts remain active. 2. Power Consumption: Reduces core power consumption, but peripherals may still consume significant power. 2.Power-down Mode: 1. Description: Enters a deeper sleep state where the processor disables clocks to peripherals and reduces core voltage. 2. Power Consumption: Minimizes power consumption to extend battery life significantly. 3.Wake-up Mechanisms: 1. Typically requires external interrupts or events to wake up from sleep modes. 2. Wake-up time can vary depending on the specific implementation and configuration. 06-08-2024 Parul Mathur 142  5.Sleep mode ❑The Cortex power management scheme supports these three sleeping modes. ❑ sleep Now, ❑ sleep on exit via Nvic, (exits the lowest-priority ISR( Interrupt Service Routine) ) and ❑ Sleepdeep modes 06-08-2024 Parul Mathur 143  5.Sleep mode Cortex-M3 Sleep Modes 1.Sleep Mode: 1. Description: In Sleep mode (or Sleep-on-Exit mode), the Cortex-M3 halts execution, allowing the processor to conserve power. 2. Power Consumption: Significantly reduces power consumption while maintaining the state of the processor. 3. Wake-up Mechanisms: Wakes up on any interrupt, enabling quick response to external events. 2.Deep Sleep Mode: 1. Description: Offers a deeper power-down state compared to Sleep mode. 2. Power Consumption: Further reduces power consumption by shutting down clocks to the processor core and peripherals. 3. Wake-up Mechanisms: Typically requires specific wake-up sources configured through peripherals or external signals. 3.Low-power Modes and Options: 1. Cortex-M3 processors often include multiple low-power modes and options, such as Sleep, Deep Sleep, and Standby modes. 2. These modes are highly configurable, allowing developers to tailor power management strategies based on application requirements. 06-08-2024 Parul Mathur 144  5.Sleep mode Key Differences Flexibility and Efficiency: Cortex-M3 processors offer more granular control over power management with multiple sleep modes and efficient wake-up mechanisms, compared to the simpler sleep modes of ARM7 processors. Performance vs. Power Trade-off: Cortex-M3 emphasizes real- time responsiveness with quick wake-up times from Sleep mode, whereas ARM7 may have slightly longer wake-up times depending on the mode and implementation. Peripheral Handling: Cortex-M3 processors typically provide finer control over peripheral states in sleep modes, optimizing power consumption across the entire system. 06-08-2024 Parul Mathur 145  5.Sleep mode 06-08-2024 Parul Mathur 146 06-08-2024 Parul Mathur 147 06-08-2024 Parul Mathur 148 06-08-2024 Parul Mathur 149 06-08-2024 Parul Mathur 150 06-08-2024 Parul Mathur 151 06-08-2024 Parul Mathur 152 06-08-2024 Parul Mathur 153 06-08-2024 Parul Mathur 154 06-08-2024 Parul Mathur 155 06-08-2024 Parul Mathur 156 06-08-2024 Parul Mathur 157  6.Memory Protection Unit ❑ARM7: Limited memory protection features. ❑ARM Cortex: Integrates Memory Protection Unit (MPU) and TrustZone technology, enabling developers to create more secure and reliable applications by isolating and protecting memory regions. ❑The Memory protection unit is an optional build. With this option, the memory area can be associated with the rules defined by other processes in the application- specific process. ❑ For example, some memory can be completely blocked by other processes, while another part of memory can be read-only for some processes. ❑You can also disable the process from entering the memory area. ❑Reliability, especially real-time, has been greatly improved. 06-08-2024 Parul Mathur 158  6.Memory Protection Unit 06-08-2024 Parul Mathur 159  6.Memory Protection Unit 06-08-2024 Parul Mathur 160  6.Memory Protection Unit 06-08-2024 Parul Mathur 161 06-08-2024 Parul Mathur 162 06-08-2024 Parul Mathur 163  Privileged enable register 06-08-2024 Parul Mathur 164  7.Power Management: ARM7: Basic power management features. ARM Cortex: Enhanced power management with multiple low- power modes and features like Wake-up Interrupt Controller (WIC) and Power Management Unit (PMU), allowing developers to create more power-efficient applications. 06-08-2024 Parul Mathur 165  Cortex-M3 Power Management The Cortex-M3 was designed with modern power management features to optimize power consumption, making it well-suited for battery-operated and energy-efficient applications. 1.Low Power Modes: Sleep Mode: The processor stops executing instructions but keeps the system clock running, allowing peripherals to remain active. This mode is entered using the WFI (Wait For Interrupt) or WFE (Wait For Event) instructions. Deep Sleep Mode: The system clock is stopped, significantly reducing power consumption. The core enters this mode using the WFI or WFE instructions in combination with setting the SLEEPDEEP bit in the System Control Register (SCR). Standby Mode: The system can enter an even lower power state where only essential functions like the RTC (Real-Time Clock) remain operational. This mode typically involves external wake-up sources. 06-08-2024 Parul Mathur 166  Cortex-M3 Power Management 2.Clock Gating: Peripherals and the CPU can be clock-gated individually to reduce power consumption when. specific functions are not needed. 3.Dynamic Voltage and Frequency Scaling (DVFS): Some Cortex-M3 implementations support DVFS, which adjusts the voltage and frequency according to the workload, optimizing power consumption dynamically. 4. Sleep-on-Exit: A feature where the processor automatically enters sleep mode when exiting an interrupt service routine, reducing the overhead of repeatedly entering and exiting sleep mode during frequent interrupts. 5. Power Control Registers: The System Control Block (SCB) and the Power Control (PWR) registers provide fine-grained control over the power states and configurations of the microcontroller. 6. Integrated Features for Power Management: The Cortex-M3 integrates features such as the SysTick timer and the Nested Vectored Interrupt Controller (NVIC) to manage low-power states efficiently 06-08-2024 Parul Mathur 167  Arm 7 TDMI Power Management ARM7TDMI: 1. Basic Low Power Modes: Includes Idle and Power-Down modes Limited clock gating is supported, typically managed by the external power management unit (PMU) or specific to the microcontroller or SoC implementation. 2. Dependent on External Components: Relies heavily on external PMUs and power control logic. 3. Less Integrated Power Features: More dependent on specific microcontroller or SoC implementations for power management capabilities. 4.Limited Power Management: Less sophisticated compared to modern microcontrollers like the Cortex-M3. 06-08-2024 Parul Mathur 168  8.Debugging and Trace: Debug Debugging involves identifying, analyzing, and fixing bugs or issues within the software or hardware. The primary goal of debugging is to understand why a program is not functioning as expected and to correct those issues. Trace Tracing involves recording the execution flow and events of a program over time, providing a detailed log of what happened during program execution. The primary goal of tracing is to analyze the program behavior, performance, and timing relationships. https://www.youtube.com/watch?v=xJ78nq_L6dM Webinar – Debug and Trace on Cortex-M4 based Microcontrollers with winIDEA & BlueBox Tools https://www.youtube.com/watch?v=lM X-2lrv7Zs Multi-core debugging with MDK 07-08-2024 Parul Mathur 169  8.Debugging and Trace: Note: SWD (Serial Wire Debug) JTAG ("Joint Test Action Group") 07-08-2024 Parul Mathur 170  8.Debugging and Trace: 07-08-2024 Parul Mathur 171 https://www.youtube.com/watch?v=xJ78nq_L6dM 07-08-2024 Parul Mathur 172  8.Debugging and Trace: Unlike traditional ARM7 or ARM9, the debugging system of the Cortex-M3 processor is based on the CoreSight Debug Architecture. Traditionally, ARM processors provide a JTAG interface, allowing registers to be accessed and memory interface to be controlled. In the Cortex-M3, the control to the debug logic on the processor is carried out via a bus interface called the Debug Access Port (DAP), which is similar to APB(Advanced Peripheral Bus) in AMBA. The DAP is controlled by another component that converts JTAG or Serial-Wire into the DAP bus interface protocol. 08-08-2024 Parul Mathur 173 08-08-2024 Parul Mathur 174  8.Debugging and Trace: ARM7: Basic debugging support. ARM Cortex: Extensive debugging and trace capabilities through CoreSight technology, including ETM (Embedded Trace Macrocell) and DWT (Data Watchpoint and Trace), providing developers with powerful tools for debugging and performance analysis. 07-08-2024 Parul Mathur 175  8.Debugging and Trace: The Cortex-M3 processor provides a comprehensive debugging environment. Based on the nature of operations, the debugging features can be classified into two groups: 06-08-2024 Parul Mathur 176  8.Debugging and Trace: 06-08-2024 Parul Mathur 177 08-08-2024 Parul Mathur 178 08-08-2024 Parul Mathur 179 08-08-2024 Parul Mathur 180 08-08-2024 Parul Mathur 181 08-08-2024 Parul Mathur 182 08-08-2024 Parul Mathur 183 08-08-2024 Parul Mathur 184 08-08-2024 Parul Mathur 185 08-08-2024 Parul Mathur 186 08-08-2024 Parul Mathur 187 08-08-2024 Parul Mathur 188 08-08-2024 Parul Mathur 189 06-08-2024 Parul Mathur 190 07-08-2024 Parul Mathur 191 08-08-2024 Parul Mathur 192  SWO is Serial Wire Output 07-08-2024 Parul Mathur 193 https://www.youtube.com/watch?v=9ScZIdgSgQ8 07-08-2024 Parul Mathur 194 07-08-2024 Parul Mathur 195 Hardware trace refers to tracing features that rely on dedicated hardware components within the microcontroller. These components capture detailed information about the system's operation with minimal impact on the microcontroller's performance. 08-08-2024 Parul Mathur 196 The two primary hardware trace components in the Cortex-M3 are: Embedded Trace Macrocell (ETM)( STM32F4 series)/Micro Trace Buffer (MTB) (MSP432) Data Watchpoint and Trace (DWT) 08-08-2024 Parul Mathur 197 06-08-2024 Parul Mathur 198 08-08-2024 Parul Mathur 199 08-08-2024 Parul Mathur 200 08-08-2024 Parul Mathur 201 08-08-2024 Parul Mathur 202 08-08-2024 Parul Mathur 203 08-08-2024 Parul Mathur 204 08-08-2024 Parul Mathur 205 Software trace refers to tracing mechanisms that involve the active participation of the software being debugged. This typically involves adding special instructions or function calls in the code to log information or track events. The primary component used for software tracing in Cortex-M3 is: Instrumentation Trace Macrocell (ITM) 08-08-2024 Parul Mathur 206 08-08-2024 Parul Mathur 207 06-08-2024 Parul Mathur 208 06-08-2024 Parul Mathur 209 06-08-2024 Parul Mathur 210  9. Floating point unit ARM7: Relies on software emulation for floating-point operations, lacking integrated hardware FPU support. This approach may be adequate for applications with modest floating-point needs. Cortex-M3 (with FPU): Offers hardware-accelerated single-precision floating-point support, providing superior performance and efficiency for applications requiring intensive floating-point computations. 06-08-2024 Parul Mathur 211 06-08-2024 Parul Mathur 212 06-08-2024 Parul Mathur 213 06-08-2024 Parul Mathur 214 06-08-2024 Parul Mathur 215 06-08-2024 Parul Mathur 216  11.Compatibility and Scalability: ❑The Cortex architecture ensures compatibility and scalability, allowing developers to migrate their applications across different Cortex cores with minimal changes, thus protecting their software investment and enabling scalable product development. 06-08-2024 Parul Mathur 217 06-08-2024 Parul Mathur 218 06-08-2024 Parul Mathur 219 06-08-2024 Parul Mathur 220 06-08-2024 Parul Mathur 221 06-08-2024 Parul Mathur 222 06-08-2024 Parul Mathur 223 06-08-2024 Parul Mathur 224 06-08-2024 Parul Mathur 225 06-08-2024 Parul Mathur 226 06-08-2024 Parul Mathur 227  ❑Program Status Registers (PSRs) ❑The program status registers are subdivided into three status registers: ✓ Application PSR (APSR)1 ✓Interrupt PSR (IPSR) ✓Execution PSR (EPSR) ❑The three PSRs can be accessed together or separately using the special register access instructions MSR and MRS. When they are accessed as a collective item, the name xPSR is used. 06-08-2024 Parul Mathur 228  Masking interrupts means disabling interrups 06-08-2024 Parul Mathur 229  The PRIMASK and BASEPRI registers are useful for temporarily disabling interrupts in timing-critical tasks. An OS could use FAULTMASK to temporarily disable fault handling when a task has crashed. In this scenario, a number of different faults might be taking place when a task crashes. Once the core starts cleaning up, it might not want to be interrupted by other faults caused by the crashed process. Therefore, the FAULTMASK gives the OS kernel time to deal with fault conditions. 06-08-2024 Parul Mathur 230  Masking Interup 06-08-2024 Parul Mathur 231  Main Stack Pointer (MSP) and the Process Stack Pointer (PSP). 06-08-2024 Parul Mathur 232  Operating modes Thread mode(privileged or unprivileged mode), Handler(Previleged) 06-08-2024 Parul Mathur 233 06-08-2024 Parul Mathur 234 06-08-2024 Parul Mathur 235 06-08-2024 Parul Mathur 236 06-08-2024 Parul Mathur 237  Privileged Mode 1.Definition: 1. In Privileged Mode, the processor has full access to all system resources, including special registers, memory regions, and peripherals. 2. This mode is typically used by the operating system kernel, interrupt service routines (ISRs), and system-level tasks. 2.Capabilities: 1. Full access to control registers, system control space, and memory protection unit (MPU) configurations. 2. Can execute all instructions, including those that affect the system configuration and hardware state. 3. Can access all memory regions, including those restricted to privileged access only. User Mode (Unprivileged Mode) 1.Definition: 1. In User Mode, the processor has limited access to system resources to prevent accidental or malicious disruptions to the system. 2. This mode is typically used by application code and tasks that do not require full access to hardware resources. 2.Capabilities: 1. Restricted access to certain control registers and system functions. 2. Limited access to memory regions and peripherals, as configured by the MPU. 3. Can execute a subset of instructions, with some system-level instructions being inaccessible. 06-08-2024 Parul Mathur 238  Switching Between Modes Supervisor Call (SVC): The SVC instruction can be used to switch from User Mode to Privileged Mode. This is typically handled through a system call mechanism where user applications request services from the operating system. Configuration: The CONTROL register in the Cortex-M3 processor includes a bit (the nPRIV bit) that indicates the current privilege level: Setting nPRIV to 1 switches the processor to User Mode. Setting nPRIV to 0 switches the processor to Privileged Mode. 06-08-2024 Parul Mathur 239  CONTROL Register 1.Purpose: The CONTROL register is used to configure the processor's privilege level and stack pointer usage. 2.Contents: The CONTROL register has several bits, but the two primary ones related to privilege level and stack pointer are: CONTROL (nPRIV): Determines the privilege level. 0: Privileged mode. 1: Unprivileged mode. CONTROL (SPSEL): Selects the stack pointer. 0: Use Main Stack Pointer (MSP). 1: Use Process Stack Pointer (PSP). 3.Usage: The CONTROL register is typically modified by the operating system to switch between privilege levels and to select the appropriate stack pointer for different contexts (e.g., system tasks vs. user tasks). Changing the CONTROL register is a way to control whether the processor is in privileged or unprivileged mode directly. 06-08-2024 Parul Mathur 240  Supervisor Call (SVC) 1.Purpose: 1. The SVC mechanism is used to request system-level services from unprivileged code by triggering an exception that is handled in privileged mode. 2.Mechanism: 1. When an SVC instruction is executed, it generates an SVC exception, causing the processor to switch to privileged mode and execute the SVC handler. 2. The SVC handler can then perform the requested privileged operation and return to the unprivileged code once done. 3.Usage: 1. SVC is typically used to implement system calls in an operating system, allowing user applications to perform operations that require elevated privileges. 2. The SVC handler examines the immediate value provided with the SVC instruction to determine the requested service. 06-08-2024 Parul Mathur 241  Summary CONTROL Register: Used by the operating system to set the processor’s privilege level and stack pointer selection. It is a low-level control mechanism for managing execution modes. SVC (Supervisor Call): Used by unprivileged code to request system services that require privileged operations. It triggers an exception handled in privileged mode, offering a secure way to elevate privileges temporarily. Both mechanisms are essential for ensuring secure and efficient execution in the Cortex-M3 processor, but they serve different purposes and are used in different contexts. 06-08-2024 Parul Mathur 242 06-08-2024 Parul Mathur 243 Built-In Nested Vectored Interrupt Controller ❑The Cortex-M3 processor includes an interrupt controller called the Nested Vectored Interrupt Controller (NVIC). It is closely coupled to the processor core and provides a number of features: ❖Nested interrupt support ❖Vectored interrupt support ❖Dynamic priority changes support ❖Reduction of interrupt latency ❖Interrupt masking 06-08-2024 Parul Mathur 244  ❖ Nested Interrupt Support ❑The NVIC provides nested interrupt support. All the external interrupts and most of the system exceptions can be programmed to different priority levels. ❑When an interrupt occurs,the NVIC compares the priority of this interrupt to the current running priority level. ❑If the priority of the new interrupt is higher than the current level, the interrupt handler of the new interrupt will override the current running task. 06-08-2024 Parul Mathur 245  ❖ Vectored Interrupt Support ❑ The Cortex-M3 processor has vectored interrupt support. ❑ When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is located from a vector table in memory. ❑ There is no need to use software to determine and branch to the starting address of the ISR. ❑ Thus it takes less time to process the interrupt request. 06-08-2024 Parul Mathur 246  ❖ Dynamic Priority Changes Support ❑Priority levels of interrupts can be changed by software during run time. ❑Interrupts that are being serviced are blocked from further activation until the interrupt service routine is completed, so their priority can be changed without risk of accidental reentry 06-08-2024 Parul Mathur 247  ❖ Reduction of Interrupt Latency ❑The Cortex-M3 processor also includes a number of advanced features to lower the interruptlatency. ❑ These include automatic saving and restoring some register contents, reducing delay in switching from one ISR to another and handling late arrival interrupts 06-08-2024 Parul Mathur 248  ❖ Interrupt Masking ❑Interrupts and system exceptions can be masked based on their priority level or masked completely using the interrupt masking registers BASEPRI, PRIMASK, and FAULTMASK. ❑They can be used to ensure that time-critical tasks can be fi nished on time without being interrupted. 06-08-2024 Parul Mathur 249  The Memory Map ❑The Cortex-M3 has a predefined memory map. ❑This allows the built-in peripherals, such as the interrupt controller and the debug components, to be accessed by simple memory access instructions. ❑The predefined memory map also allows the Cortex-M3 processor to be highly optimized for speed and ease of integration in system-on-a-chip (SoC) designs. ❑ Overall, the 4 GB memory space can be divided into ranges as shown in Figure 2.6. ❑The Cortex-M3 design has an internal bus infrastructure optimized for this memory usage. In addition, the design allows these regions to be used differently. ❑ For example, data memory can still be put into the CODE region, and program code can be executed from an external Random Access Memory (RAM) region. 06-08-2024 Parul Mathur 250  The Memory Map ❑ The Cortex-M3 has a predefi ned memory map. ❑ This allows the built-in peripherals, such as the interrupt controller and debug components, to be accessed by simple memory access instructions. ❑ Thus most system features are accessible in C program code. ❑ The predefined memory map also allows the Cortex-M3 processor to be highly optimized for speed and ease of integration in system-on-a-chip (SoC) designs. 06-08-2024 Parul Mathur 251  The Bus Interface There are several bus interfaces on the Cortex-M3 processor. They allow the Cortex-M3 to carry instructionfetches and data accesses at the same time. The main bus interfaces are as follows: Code memory buses System bus Private peripheral bus 06-08-2024 Parul Mathur 252  The Bus Interface ❑The code memory region access is carried out on the code memory buses, which physically consist of two buses, one called I-Code and other called D-Code. These are optimized for instruction fetches for best instruction execution speed. ❑The system bus is used to access memory and peripherals. This provides access to the Static Random Access Memory (SRAM), peripherals, external RAM, external devices, and part of the system level memory regions. ❑The private peripheral bus provides access to a part of the system-level memory dedicated to private peripherals, such as debugging components. 06-08-2024 Parul Mathur 253  Exceptions and Interrupts The Cortex-M3 supports a number of exceptions, including a fixed number of system exceptions and a number of interrupts, commonly called IRQ. The number of interrupt inputs on a Cortex-M3 microcontroller depends on the individual design. Interrupts generated by peripherals, except System Tick Timer, are also connected to the interrupt input signals. The typical number of interrupt inputs is 16 or 32. However, you might find some microcontroller designs with more (or fewer) interrupt inputs. Besides the interrupt inputs, there is also a nonmaskable interrupt (NMI) input signal. The actual use of NMI depends on the design of the microcontroller or system-on-chip (SoC) product you use. 06-08-2024 Parul Mathur 254 Exceptions and Interrupts In most cases, the NMI could be connected to a watchdog timer or a voltage-monitoring block that warns the processor when the voltage drops below a certain level The NMI exception can be activated any time, even right after the core exits reset. The list of exceptions found in the Cortex-M3 is given below. A number of the system exceptions are fault-handling exceptions that can be triggered by various error conditions. The NVIC also provides a number of fault status registers so that error handlers can determine the cause of the exceptions. 06-08-2024 Parul Mathur 255 Exceptions and Interrupts 06-08-2024 Parul Mathur 256  Stack Memory Operations In the Cortex-M3, besides normal software-controlled stack PUSH and POP, the stack PUSH and POP operations are also carried out automatically when entering or exiting an exception/interrupt handler. 06-08-2024 Parul Mathur 257 06-08-2024 Parul Mathur 258  Stack Memory Operations The stack pointer implementation in Cortex-M3 is designed to be more straightforward and efficient for embedded applications, offering better separation of user and system tasks and simplifying the context switching process compared to the ARM7 architecture. 06-08-2024 Parul Mathur 259  CORTEX M3 ❑ Cortex-M3 processor-based microcontrollers can be easily programmed using the C language and are based on a well-established architecture, application code can be ported and reused easily, reducing development time and testing costs ❑ Additionally, the Cortex-M3 processor introduces a number of features and technologies that meet the specific requirements of the microcontroller applications, such as nonmaskable interrupts for critical tasks, highly deterministic nested vector interrupts, atomic bit manipulation, and an optional Memory Protection Unit (MPU). ❑ These factors make the Cortex-M3 processor attractive to existing ARM processor users as well as many new users considering use of 32-bit MCUs in their products. 06-08-2024 Parul Mathur 260 06-08-2024 Parul Mathur 261 09-08-2024 Parul Mathur 262  Decision ❑If cost is the main consideration, you should choose cortex; If you are looking for better performance and improved power consumption at low cost, you might want to consider choosing cortex-m3, especially if your application is in the automotive and wireless areas, preferably with CORTEX-M3, This is CORETEX-M3 's main positioning market. ❑Because of the many integration elements in the CORTEX-M3 kernel and the adoption of Thumb-2 instruction set, it is easier to develop and debug than ARM7TDMI. However, it is not difficult to redefine the application of ARM7TDMI, especially in the case of using an RTOS. Conservatives may follow the ARM7TDMI kernel's chips and avoid using features that complicate the redefinition. 09-08-2024 Parul Mathur 263 09-08-2024 Parul Mathur 264 09-08-2024 Parul Mathur 265 09-08-2024 Parul Mathur 266 09-08-2024 Parul Mathur 268 09-08-2024 Parul Mathur 269 MPY (Multiplier)