Scaling Theory in VLSI Design

Scaling Theory

• Scaling involves moving very large-scale integrated (VLSI) designs to new fabrication methods, aiming to shrink circuitry size.
• Examples include a 1961 integrated circuit with two transistors, a 2001 Pentium 4 processor containing 42 million transistors, and a 2006 Itanium 2 dual processor with 1.7 billion transistors.

Why Scale?

• Improved performance: More complex systems are achievable.
• Increased transistor density: Reduces cost per transistor and system size.
• Reduced power: Smaller transistors require less supply voltage.

Scaling Predictions

• Gordon Moore predicted exponential growth in the number of transistors per integrated circuit (IC).
• He predicted a doubling of transistors every 2-3 years.
• In 1975, he predicted more than 65,000 transistors in an IC.

Timeline of Major Events

• 1947: First transistor (Bell Labs).
• 1958: First integrated circuit (Noyce/Fairchild & Kilby/Texas Instruments).
• 1968: Noyce and Moore formed Intel.
• 1971: Intel introduced the 4004.
• 2006: Intel shipped its first billion-transistor processor.

How Much Can We Shrink?

• Chip area (A) scales proportionally to 1/S², or (1/S)(1/S).

Full Scaling (Constant-Field)

• The principle involves scaling both horizontal and vertical device dimensions by the same factor (s > 1) while keeping the electric field unchanged.
• Scaling process elements by 30% is commonly used.
• Power supplies and voltage thresholds should be adjusted by 30% for full scaling.
• A scaling factor (S) between 1.2 and 1.5 has been historically common.

Scaling Effect on Device Characteristics

• Power: Static power (P) in MOSFETs is defined as P = I_DS V_DS. Both I_DS and V_DS scale with 1/S in full scaling, resulting in P scaling with 1/S².
• Power Density: Power density is power per area. It scales as 1/S² and remains constant, which can lead to heat issues as chips get larger with scaling.

Constant Voltage Scaling

• This scaling method only changes device dimensions and not voltages.
• Power scales as S, which is not desirable.
• Power density scales as S³, aggravating heat generation and thus limiting performance and scalability.

Scaling Choices

• Full scaling is favorable but sometimes impractical.
• Constant-voltage scaling can worsen performance.
• A hybrid approach combining both methodologies is often used.

Limits of Scaling

• Thermodynamics: Doping concentration in source and drain
• Physics: Tunneling through gate oxide
• Statistics: Statistical fluctuations in body doping
• Economics: Factory cost/ cost-effectiveness

About Gate Oxide Scaling

• Gate oxide thickness decreases in proportion to channel length to maintain control over the channel.
• For channel lengths below 100nm, the oxide thickness becomes thinner, limiting the number of atomic layers and reaching fundamental limits. Typical structures show that oxide thickness for 90nm Intel devices was ~1.2nm.

Tunneling through Gate Oxide

• Oxide thickness limits occur as current density (I_gate) is proportional to 1/T_ox³, and below 1.5-2.0 nm, SiO2 or Si-O-N is no longer suitable.

New Materials and Structures for Advanced MOSFETs

• Problems with using current CMOS methods:
  • poor electrostatics
  • poor channel transport
  • S/D parasitic resistance
  • gate leakage increased
  • gate depletion increased end-of-transistor effect
• Solutions:
  • Double Gate and FinFET
  • Advanced materials such as high dielectric constant (high-k) dielectrics
  • lightly doped drains (LDD)

Gate Leakage

• Conventional gate dielectrics (SiO₂) experience increased leakage with scaling.
• Alternative gate oxides, like HfO₂, are needed since the thickness of SiO₂ approaches a theoretical limit with further scaling.

High Mobility Channel:Strained Silicon

• Strained silicon enhances carrier mobility due to changes in the energy structure.

Strained Silicon

• Growing strained silicon layers over relaxed SiGe layers (which has a different crystal structure and lattice constant) can be used to control the lattice structure and thus carrier mobility.

Typical device structure

• Strained Si is one way to boost the mobility and thus current in silicon devices.
• The structure involves strained silicon over relaxed SiGe, to increase device scalability while reducing gate leakage and end-of-transistor and other critical effects.

Mobility Enhancements

• Strained Si increases NMOS and PMOS Current by ~ 1.5x, but only ~1.15x for PMOS.
• Methods like this are important to scale further.

Double-Gate MOSFET Structures

• Different architectures, such as vertical and planar, exist.
• Designs like finFETs and double-gate architectures provide more control and scalability.

Advanced MOSFET Structures

• Configurations like FinFETs and double-gate MOSFETs are examples of advanced structures.
• SOI (Silicon on Insulator) structures

Multigate MOSFET

• Advanced multi-gate MOSFET architectures improve voltage and current control.

Short Channel Effects

• Adverse effects like threshold voltage reduction and increased leakage current are due to short channel lengths
• Types: Vt roll-off (Reverse Short Channel Effect, RSCE), Drain-Induced Barrier Lowering (DIBL), Narrow-Width Effect (Inverse-Narrow-Width Effect), Channel Length Modulation, Punchthrough Effect, Breakdown, Velocity Saturation and Overshoot.