Week 3 Digital Arithmetic Operations PDF

ITS 62704 Computer Organization & Architecture Topic 3: Digital Arithmetic Operations Dr Sarerusaenye Ismail  Outline of Topic...

ITS 62704 Computer Organization & Architecture Topic 3: Digital Arithmetic Operations Dr Sarerusaenye Ismail  Outline of Topic 2 Introduction Integer Arithmetic Addition Negation Multiplication Division Floating-Point Arithmetic Floating-Point Representation 2 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Integer Arithmetic  # of Bits Range --------- ------------------------- 8 0 255 16 0 65,535 An unsigned integer is an integer without a sign. Its range is between 0 and positive infinity. Range 0 to 2^N -1 Example: 0 to 256  ::Unsigned integer representation:: Example 1 Store 7 in an 8-bit memory location. First change the number to binary 111. Solution Add five 0s to make a total of N (8) bits, 00000111. The number is stored in the memory location. Example 2 Store 258 in a 16-bit memory location. First change the number to binary 100000010. Solution Add seven 0s to make a total of N (16) bits, 0000000100000010. The number is stored in the memory location. 5 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Negation Twos complement operation Take the Boolean complement of each bit of the integer (including the sign bit) Treating the result as an+18unsigned binary = 00010010 (twos integer, complement) add 1 bitwise complement =11101101 + 1 11101110 =- 18 -18 = 11101110 The negative of the (twosnumber is itself: complement) bitwise complement =00010001 + 1 00010010 = +18 6 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Negation 1.Negation is the operation of converting a positive number to its negative equivalent or a negative number to its positive equivalent. 2.When signed binary numbers are represented in the 2’s-complement system, negation is performed simply by performing the 2’s-complement operation. 3.To illustrate, let’s start with in eight-bit +9 binary form. Its signed representation is 00001001. If we take its 2’s complement we get 11110111, which represents the signed value -9. 4.Likewise, we can start with the representation of which is 11110111, and take its 2’s complement to get 00001001, which represents +9 7 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Represent each of the following signed decimal numbers as a signed binary number in the 2’s- complement system. Use a total of five bits, including the sign bit. +13 -9 The number is positive, so the magnitude The number is negative, so the magnitude (13) will be represented in its true- (9) must be represented in 2’s complement magnitude form, that is,. Attaching the form: sign bit of 0, we have When we attach the sign bit of 1, the complete signed number becomes 8 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Addition and Subtraction Addition: On any addition, the result may be larger than can be held in the word size being used – this condition is called overflow When overflow occurs, the ALU Overflow must signal this fact so that no can occur attempt is made to use the whether or not there is result a carry ToOverflow Rule: the detect overflow, If two numbers following are added, rule is observed: and they are both positive or both negative, then overflow occurs if and only if the result has the Addition of Numbers in Twos opposite sign Complement Representation 9 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Addition and Subtraction (cont’d) Subtraction: Subtraction is easily handled with this following rule: Substraction Rule: To subtract one number (subtrahend) from another (minuend), take the twos complement (negation) of the subtrahend and add it Thus, to the minuend subtraction is achieved using addition The last 2 examples demonstrate that the overflow rule still applies Subtraction of Numbers in Twos Complement Representation (M-S) 10 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Addition and Subtraction (cont’d) Geometric Depiction of Twos Some insight into twos Complement Integers: complement addition and subtraction can be gained by looking at a geometric depiction The circle in the upper half of each part is formed by selecting the appropriate segment of the number line and joining the endpoints Note that when the numbers are laid out on a circle, the twos complement of any number is horizontally opposite that number (shown in dashed lines) Starting at any number by 11 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2 moving k positions clockwise,  Addition and Subtraction (cont’d) Here only shows data paths Hardware for addition and Controls signals are needed to control whether or not the subtraction: complementer is used, depending The data paths and hardware elements on whether the operation is needed to accomplish addition and addition or subtraction subtraction The central element is a binary adder, which is presented two numbers for addition and produces a sum and an overflow indication The binary adder treats the 2 numbers as unsigned integers For addition, the 2 numbers are presented to the adder from 2 registers (designated here case A and B registers) The result may be stored in one of these registers or in a third The overflow indication is stored in a 1-bit 12 overflow 11/20/2024 flag COMPUTER BIT1123 (0 = no ORGANIZATION overflow; 1&=ARCHITECTURE: Topic 2  Multiplication Multiplication of Unsigned Binary Integers: 13 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Multiplication (cont’d) Hardware Implementation of Unsigned Binary Multiplication: 14 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Multiplication (cont’d) Comparison of Multiplication of Unsigned and Twos Complement Integers: 15 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Multiplication (cont’d) Booth’s Algorithm for Twos Complement Multiplication: 16 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Multiplication (cont’d) Example of Booth’s Algorithm (7 x 3) Example using Booth’s Algorithm 17 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Division Example of Division of Unsigned Binary Integers Example of Restoring Twos Complement Division (7 / 3) 18 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Floating- Point Representati on  Principles With a fixed-point notation it is possible to represent a range of positive and negative integers centered on or new 0 By assuming a fixed binary or radix point, this format allows the representation of numbers with a fractional component as well Limitations: Very large numbers cannot be represented nor can very small fractions The fractional part of the quotient in a division of two large numbers could be lost 20 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Floating- Point Arithmetic  Floating-Point Numbers and Arithmetic A floating-point Operations operation may produce one of these conditions: Exponent overflow: A positive exponent exceeds the maximum possible exponent value In some systems, this may be designated as +  or -  Exponent underflow: A negative exponent is less than the 22 minimum 11/20/2024 possible BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Floating-Point Addition and Subtraction In floating-point arithmetic, addition and subtraction are more complex than multiplication and division, A step-by-step narrative because of the need for alignment highlights the main functions required for floating-point There are 4 basic phases of the addition and subtraction algorithm for addition and For the addition or subtraction: subtraction operation, the 2 1. Check for zeros operands must be 2. Align the significands transferred to registers that will be used by the ALU 3. Add or subtract the significands 4. Normalize the result If the floating-point format includes an implicit significand bit, that bit must 23 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2 be made explicit for the  Phase 3. Addition: Floating-Point Addition The 2 significands are added together, taking into account their signs. Because the signs may differ, the result may be 0. and Subtraction (cont’d) Phase 2. Significand alignment: There is also the possibility of significand overflow by 1 digit. If so, the significand of the result is shifted right and the Manipulate the exponent is incremented. numbers so that the 2 An exponent overflow could occur as a result; this would be exponents are equal reported and the operation halted. Phase 1. Zero check: Because addition and subtraction are identical Phase 4. Normalization: except for a The final phase normalizes the sign change, result. Normalization consists the process of shifting significand digits begins by left until the most significant changing the digit (bit, or 4 bits for base-16 sign of the exponent) in non-zero. subtrahend if Each shift causes a decrement it is a of the exponent and thus subtract could cause an exponent operation. underflow. Next, if Finally, the result must be either Floating-Point Addition rounded off and then reported. operand is 0, and Subtraction (Z  X  Y) We defer a discussion of the other is rounding until after a reported 24 as 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2 discussion of multiplication  Floating-Point Multiplication and Division Floating-Point Floating-Point Multiplication Division (Z  X x Y) (Z  X / Y) 25 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Precision Considerations Guard Bits The use of Guard Bits 26 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Precision Considerations (cont’d) Rounding IEEE Standard Approaches: Round to nearest: The result is rounded to the nearest representable number Round toward +: The result is rounded up toward plus infinity Round toward -: The result is rounded down toward negative infinity Round toward 0: The result is rounded toward zero 27 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Precision Considerations (cont’d) Interval Arithmetic Provides an efficient method for Minus infinity and rounding to monitoring and controlling errors in plus are useful in floating-point computations by implementing interval producing two values for each result arithmetic The two values correspond to the lower and upper endpoints of an Truncation interval that contains the true result Round toward zero The width of the interval indicates Extra bits are ignored the accuracy of the result Simplest technique If the endpoints are not A consistent bias toward zero representable then the interval in the operation endpoints are rounded down and up Serious bias because it affects respectively every operation for which there If the range between the upper and are non-zero extra bits 28 lower BIT1123 11/20/2024 bounds is sufficiently COMPUTER narrow ORGANIZATION & ARCHITECTURE: Topic 2 Tutorial 3  Exercises / Discussion 1.Briefly explain the following representations: sign magnitude, twos complement, biased. 2.Explain how to determine if a number is negative in the following representations: sign magnitude, twos complement, biased. 3.Briefly explain the drawbacks of sign-magnitude representation. 4.How can you form the negation of an integer in twos complement representation? 5.In general terms, when does the twos complement operation on an n-bit integer produce the same integer? 6.What is the difference between the twos complement representation of a number and the twos complement of a 30 number? 11/20/2024 BIT1123 COMPUTER ORGANIZATION & ARCHITECTURE: Topic 2  Thanks! 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