Basic Structure of Computers PDF

BASIC STRUCTURE OF COMPUTERS BASIC CONCEPTS Computer Architecture (CA) is concerned with the structure and behaviour of the computer. CA includes the information formats, the instruction set and techniques for addressing memory. In general covers, CA covers 3 aspects of computer-design na...

BASIC STRUCTURE OF COMPUTERS BASIC CONCEPTS Computer Architecture (CA) is concerned with the structure and behaviour of the computer. CA includes the information formats, the instruction set and techniques for addressing memory. In general covers, CA covers 3 aspects of computer-design namely: 1) Computer Hardware, 2)Instruction set Architecture and 3) Computer Organization. 1. ComputerHardware  It consists of electronic circuits, displays, magnetic and optical storage media and communication facilities. 2. Instruction Set Architecture  It is programmer visible machine interface such as instruction set, registers, memory organization and exception handling.  Two main approaches are 1) CISC and 2)RISC. (CISC: Complex Instruction Set Computer, RISC: Reduced Instruction Set Computer) 3. Computer Organization  It includes the high level aspects of a design, such as → memory-system → bus-structure & → design of the internal CPU.  It refers to the operational units and their interconnections that realize the architectural specifications.  It describes the function of and design of the various units of digital computer that store and process information. FUNCTIONAL UNITS A computer consists of 5 functionally independent mainparts: 1) Input 2) Memory 3) ALU 4) Output& 5) Control units. 1  1. Input Unit : The input unit consists of devices like keyboard,mouse etc which accept information from user and convert it into coded format. The CPU accepts this coded data and performs operations. 2. Memory :The term memory refers to storage space in computer system. There are two classes of storage :  Primary Memory  Secondary Memory Primary Memory ( Semiconductor memory or Main Memory) The information is stored as group of bits. Group of 8 bits is called byte. Group of16 bits is called Word. RWM: Able to store and retrieve information (Read/Write ).Commonly called RAM (Random access memory) ROM ( Read Only Memory ): Information can only be retrieved. Write is not possible. Volatile Memory: It Can retain the data only as long as power is applied.Once power supply is switched off ,content s of memory are lost.Hence primary memory is volatile. Secondary Memory : Ex magnetic tape, drum, magnetic disk,CDROMs,DVD  Nonvolatile  Large storage capacity (Bulk storage) 3. ALU: All arithmetic and logical operations are carried out by ALU. CPU has has its own storage called registers for temporary storage of data and results. 4. Output Unit : The processed data is sent to outside world through output unit. CRT,Printer, LED/LCD display etc are output evices. Output Unit transforms Digital data sent by CPU into a form that is understood by the user. The output of processor may be converted into text,audio or video depending on application 5. Control unit: CU is responsible for issuing appropriate control signals to ALU, Memory etc and to synchronize all the activities in computer system.It governs the actual timing of all the operations like data transfers between registers and memory,arithmetic and logic operations inside ALU. The CU works with areference signal called processor called processor clock.To execute a machine instruction ,processor divides the action to be performed into sequence of basic steps where each basic step is said to be completed in one clock cycle. Central Processing Unit ( CPU): It is called brain of computer. It is responsible for all computations and processing activities on the information received.. The processed data may be 2 sent to output unit or stored in memory for future use. The CPU mainly consists of 3 functional Parts  Arithmetic Logic Unit ( ALU )  Timing & Control unit  Set of Registers ALU(Arithmetic Register Array Logic Unit) Timing & Control unit Block diagram of a Processor 3  BASIC OPERATIONAL CONCEPTS: Fig shows Interconnection of CPU and memory buses. The memory stores the information relevent to task to be performed. The information is stored as a binary pattern of 0s and 1s.in every location sequentially. The information may be data(operand) or instruction. MAIN PARTS OF PROCESSOR The processor contains ALU, control-circuitry and many registers. The processor contains n general-purpose registers R0 through Rn-1. These registers are used for temporarily storing data and results bof any computation. The IR ( Insruction Register) holds the instruction that is currently being executed. The instruction code is passed to the instruction decoder in CU and then decoded to generate timing signals for different operations. The Control-Unit Generates the timing-signals that determine when a given action is to take place. The PC(Program Counter) contains the memory-address of the next-instruction to be fetched & executed. During the execution of an instruction,the contents of PC are automatically updated to point to next instruction. The MAR(Memory Address Register) holds the address of the memory-location to be accessed. The MDR (Memory Data Register) contains the data to be written into or read out of the addressed location. MAR and MDR facilitates the communication with memory. Memory AR MAR MDR Timing & Control Unit R0 PC R1. Arithmetic. Logic Unit. (ALU) IR Rn-1 Fig : Interconnection between Processor and Memory 4 Steps To Execute An Instruction The complete operation in computer is governed by the instructions stored in memory. The steps involved in execution of instruction are: 1) The execution of program starts by loading the address of first instruction (to be executed) into PC. 2) The contents of PC (i.e. address) are transferred to the MAR & address is sent out on address bus. The control-unit issues Read control signal to memory to read instruction code.and it is stored in IR. Simultaneously contents of PC are incremented to point to next instruction in the program. 3) The instruction code is decoded to decide about operation. If data needed for operation is already available in general purpose registers , the operation is immediately carried out. 4) If operands reside in memory then respective addresses are are sent from MAR to memory and data are read into MDR one by one.. From MDR they are directly passed to ALU or to any other general purpose register in processor as needed. Then operation is performed by ALU. 5) If the result of this operation is to be stored in the memory, then the result is sent to the MDR. The address of the location where the result is to be stored is sent to the MAR and a Write control signal is issued by CU and result is stored in memory.. Memory AR MAR MDR Timoing & Control Unit R0 PC R1 Arithmetic Logic Unit (ALU) IR Rn-1 Fig : Interconnection between Processor and Memory Normal execution of program may preempted (suspended and later resumed) if internally or externally initiated emergency condition exists. In such case the execution of of current program is said to be interrupted. Interrupt is a request from I/O device for service by the processor. 5  The request is granted by executing an interrupt service routine.(ISR) Before executing ISR status of processor like contents of PC, registers and control information is saved in amemory area called STACK. When ISR execution is completed the status of processor is restored and normal execution continues. Examples : An Instruction consists of 2 parts 1) Operation code (Opcode) 2) Operands. OPCODE OPERANDS The data/operands are stored in memory. The individual instruction are brought from the memory to the processor. Then, the processor performs the specified operation. Let us see a typical instruction ADD LOCA, R0 This instruction is an addition operation. The following are the steps to execute the instruction: Step 1: Fetch the instruction from main-memory into the processor. Step 2: Fetch the operand at location LOCA from main-memory into the processor. Step 3: Add the memory operand (i.e. fetched contents of LOCA) to the contents of register R0. Step 4: Store the result (sum) in R0. The same instruction can be realized using 2 instructions as: LOAD LOCA, R1 ADD R1, R0 The following are the steps to execute the instruction: Step 1: Fetch the instruction from main-memory into the processor. Step 2: Fetch the operand at location LOCA from main-memory into the register R1. Step 3: Add the content of Register R1 and the contents of register R0. Step 4: Store the result (sum) in R0. 6  BUS STRUCTURE All the functional units are connected using group of lines called bus. A bus is a group of lines( wires) which carry information from source to destination , in the form of electrical signals. Bus serves as a connecting path for several devices. The bus ( group of wires or lines ) carry data or address or control signals. There are 2 types of Bus structures: 1. Single Bus Structure 2. Multiple BusStructure. 1) Single Bus Structure  Because the bus can be used for only one transfer at a time, only 2 units can actively use the bus at any given time.  Bus control lines are used to arbitrate multiple requests for use of the bus.  Advantages: 1) Low cost & 2) Flexibility for attaching peripheral devices. Input Output Memory Processor Fig : Single bus structure The devices connected to a bus vary widely in their speed of operation. To synchronize their operational-speed, buffer-registers can be used. Buffer Registers → are included with the devices to hold the information during transfers. → prevent a high-speed processor from being locked to a slow I/O device during data transfers. The system bus usually has 3 parts : Data Bus : It is used to carry data(operand ) from input device or memory to the processor. It is also used to transfer transfer data (result of operation) from processor to memoryor output device. Hence it is bidirectional bus. Address Bus :The processor uses this bus to access the memory or any I/O device connected to it. The processor sends address of memory or I/O device on address bus. Hence it is unidirectional bus. Control Bus :For synchronizing various activities such as read, write,reset etc the processor needs signals to inform the devices about any activity. Hence control lines are needed. In some cases external 7  devices also can initiate an activity. Hence it is bidirectional bus.The control bus is a set of indidual signals carrying information at different instants of time. The complete bus structure is shown in figure Input Output Unit Unit Address Bus Processor Data bus Bus Data Bus Control Bus Memory Fig : Single bus structure showing the details of connection. 2) MultipleBus Structure For greater performance Multiple Bus Structure may be used. For Ex , in 2-bus structure two operands required for arithmetic operation could be fetched simultaneously over two buses. This is not possible with a single bus structure.  Systems that contain multiple buses achieve more concurrency in operations.  Two or more transfers can be carried out at the same time.  Advantage: Better performance.  Disadvantage: Increased cost. 8  RISC & CISC Based on instruction set computers may be classified into 2 categories  RISC : Reduced Instruction set Computer  CISC : Complex Instruction set Computer Following table gives the differences between RISC and CISC computers RISC ( Reduced Instruction set CISC (Complex Instruction set Computer) SL.No Computer ) Very few instructions are present. The number of instructions is generally less A large number of instructions are present in 1 than 100. the architecture. 2 Simple instructions taking one cycle. Complex instructions taking multiple cycle. Instructions are executed by Instructions are executed by 3 hardwired control unit. microprogrammed control unit. 4 Few instructions. Many instructions. 5 Fixed format instructions. Variable format instructions. Few addressing modes, and most 6 instructions have register to register Many addressing modes. addressing mode. Arithmetic and logical operations only use register operands. Memory referencing is only allowed by Arithmetic and logical operations can be 7 loading and storing instructions, i.e. applied to both memory and register reading from memory into a register operands. and writing from a register to memory respectively. Single register set. 8 Multiple register set. CISC supports array. 9 RISC does not support an array. Registers are being used for procedure The stack is being used for procedure 10 arguments and return addresses. arguments and returns addresses. 11 No pipelined or less pipelined. Highly pipelined. EX: SPARC, POWER PC Ex: Intel architecture, AMD 9  MEMORY-LOCATIONS & ADDRESSES Memory consists of many millions of storage cells (flip-flops). Each cell can store a bit of information i.e.0or1(Figure2.1). Each group of n bits is referred to as a word of information, and n is called the word length. The word length can vary from 8 to 64bits. A unit of 8 bits is called a byte. Accessing the memory to store or retrieve a single item of information (word/byte) requires distinct addresses for each item location.(It is customary to use numbers from 0 through 2k-1 as the addresses of successive-locations in the memory). If 2k= no. of addressable locations; then 2kaddresses constitute the address-space of the computer. For example, a 24-bit address generates an address-space of 224 locations (16 MB). 10  BYTE-ADDRESSABILITY In byte-addressable memory, successive addresses refer to successive byte locations in the memory. Byte locations have addresses 0, 1, 2.... If the word-length is 32 bits, successive words are located at addresses 0, 4, 8.. with each word having 4 bytes. BIG-ENDIAN & LITTLE-ENDIAN ASSIGNMENTS There are two ways in which byte-addresses are arranged (Figure2.3). 1) Big-Endian: Lower byte-addresses are used for the more significant bytes of the word. 2) Little-Endian: Lower byte-addresses are used for the less significant bytes of the word In both cases, byte-addresses 0, 4, 8.................are taken as the addresses of successive words in the memory. Example 1 : Consider a 32-bit integer (in hex): 0x12345678 which consists of 4bytes: 12,34,56,and78.  Hence this integer will occupy 4 bytes in memory.  Assume, we store it at memory address starting1000.  On little-endian, memory will look like Address Value 1000 78 1001 56 1002 34 1003 12 11   On big-endian, memory will look like Address Value 2000 12 2001 34 2002 56 2003 78 Example 2 : Consider a 32-bit integer (in hex): 0x98765432 which consists of 4bytes: 98,76,54, and 32  Hence this integer will occupy 4 bytes in memory.  Assume, we store it at memory address starting 2000.  On little-endian, memory will look like Address Value 2000 32 2001 54 2002 76 2003 98  On big-endian, memory will look like Address Value 1000 98 1001 76 1002 54 1003 32 WORD ALIGNMENT Words are said to be Aligned in memory if they begin at a byte-address that is a multiple of the number of bytes in a word. For example, If the word length is16 (2 bytes),aligned words begin at byte-addresses 0,2,4..... If the word length is 64 (2 bytes),aligned words begin at byte-addresses 0,8,16..... Words are said to have Unaligned Addresses, if they begin at an arbitrary byte-address. 12 ACCESSING NUMBERS, CHARACTERS & CHARACTERS STRINGS A number usually occupies one word. It can be accessed in the memory by specifying its word address. Similarly, individual characters can be accessed by their byte-address. There are two ways to indicate the length of the string: 1) A special control character with the meaning "end of string" can be used as the last character in the string. 2) A separate memory word location or register can contain a number indicating the length of the string in bytes. MEMORY OPERATIONS Two memory operations are: 1) Load (Read/Fetch) & 2) Store (Write). The Load operation transfers a copy of the contents of a specific memory-location to the processor. The memory contents remain unchanged. Steps for Load operation: 1) Processor sends the address of the desired location to the memory. 2) Processor issues „read ‟signal to memory to fetch the data. 3) Memory reads the data stored at that address. 4) Memory sends the read data to the processor. The Store operation transfers the information from the register to the specified memory-location. This will destroy the original contents of that memory-location. Steps for Store operation are: 1) Processor sends the address of the memory-location where it wants to store data. 2) Processor issues write ‟signal to memory to store the data. 3) Content of register (MDR) is written into the specified memory-location. INSTRUCTIONS & INSTRUCTION SEQUENCING A computer must have instructions capable of performing 4 types of operations: 1) Data transfers between the memory and the registers (MOV, PUSH, POP,XCHG). 2) Arithmetic and logic operations on data (ADD, SUB, MUL, DIV, AND, OR,NOT). 3) Program sequencing and control (CALL.RET, LOOP,INT). 4) I/0 transfers (IN,OUT). 13  REGISTER TRANSFER NOTATION (RTN) The possible locations in which transfer of information occurs are: 1) Memory-location 2) Processor register & 3) Registers in I/O device. Location Hardware Binary Address Example Description Memory LOC, PLACE, NUM R1 [LOC] Contents of memory-location LOC are transferred into register R1. Processor R0, R1 ,R2 [R3]  [R1]+[R2] Add the contents of register R1 & R2 and places their sum into R3. I/O Registers DATAIN, DATAOUT R1 DATAIN Contents of I/O register DATAIN are transferred into register R1. ASSEMBLY LANGUAGE NOTATION To represent machine instructions and programs, assembly language format is used. Assembly Language Format Description Move LOC, R1 Transfer data from memory-location LOC to register R1. The contents of LOC are unchanged by the execution of this instruction, but the old contents of register R1 are overwritten. Add R1, R2, R3 Add the contents of registers R1 and R2, and places their sum into register R3. BASIC INSTRUCTION TYPES There are 4 instruction types : 1. Three Address instruction 2. Two Address instruction 3. One Address instruction 4. Zero address instruction Table gives syntax example and description of instructions. 14  BASIC INSTRUCTION TYPES Instruction Syntax Example Description Instruction Type for Operation C0. During each pass, → address of the next list entry is determined and → that entry is fetched and added to R0. The instruction Decrement R1 reduces the contents of R1 by 1 each time through the loop. Then Branch Instruction loads a new value into the program counter. As a result, the processor fetches and executes the instruction at this new address called the Branch Target. A Conditional Branch Instruction causes a branch only if a specified condition is satisfied. If the condition is not satisfied, the PC is incremented in the normal way, and the next instruction in sequential address order is fetched and executed. CONDITION CODES The processor keeps track of information about the results of various operations. This is accomplished by recording the required information in individual bits, called Condition Code Flags. These flags are grouped together in a special processor-register called the condition code register (or status 18  register). Four commonly used flags are: N (negative) set to 1 if the result is negative, otherwise cleared to 0. Z (zero) set to 1 if the result is 0; otherwise, cleared to0. V (overflow) set to 1 if arithmetic overflow occurs; otherwise, cleared to 0. C (carry) set to 1 if a carry-out results from the operation; otherwise cleared to0. 19  ADDRESSING MODES The different ways in which the location of an operand is specified in an instruction are referred to as Addressing Modes (Table 2.1). IMPLEMENTATION OF VARIABLE AND CONSTANTS Variable is represented by allocating a memory-location to hold its value. Thus, the value can be changed as needed using appropriate instructions. There are 2 accessing modes to access the variables: 1) RegisterMode 2) Absolute Mode Register Addressing Mode The operand is the contents of a register. The name (or address) of the register is given in the instruction. Registers are used as temporary storage locations where the data in a register are accessed. For example, the instruction Move R1, R2 ;Copy content of register R1 into register R2. Absolute (Direct) Addressing Mode The operand is in a memory-location. The address of memory-location is given explicitly in the instruction. The absolute mode can represent global variables in the program. For example, the instruction Move LOC, R2 ;Copy content of memory-location LOC into register R2. 20 Immediate Addressing Mode The operand is given explicitly in theinstruction. For example, the instruction Move #200, R0 ;Place the value 200 in registerR0. Clearly, the immediate mode is only used to specify the value of a source-operand. INDIRECTION AND POINTERS Instruction does not give the operand or its address explicitly. Instead, the instruction provides information from which the new address of the operand can be determined. This address is called Effective Address (EA) of the operand. Indirect Addressing Mode The EA of the operand is the contents of a register(or memory-location). The register (or memory-location) that contains the address of an operand is called aPointer. We denote the indirection by → name of the register or → new address given in the instruction. E.g: Add (R1),R0;The operand is in memory. Register R1 gives the effective-address(B) of the operand. The data is read from location B and added to contents of register R0. To execute the Add instruction in fig 2.11 (a), the processor uses the value which is in register R1, asthe EA of the operand. It requests a read operation from the memory to read the contents of location B. The value read isthe desired operand, which the processor adds to the contents of registerR0. Indirect addressing through a memory-location is also possible as shown in fig 2.11(b). In this case,the processor first reads the contents of memory-location A, then requests a second read operationusing the value B as an address to obtain theoperand. 21 Program Explanation In above program, Register R2 is used as a pointer to the numbers in the list, and the operands are accessed indirectly through R2. The initialization-section of the program loads the counter-value n from memory-location N into R1 and uses the immediate addressing-mode to place the address value NUM1, which is the address of the first number in the list, into R2. Then it clears R0 to 0. The first two instructions in the loop implement the unspecified instruction block starting at LOOP. The first time through the loop, the instruction Add (R2), R0 fetches the operand at location NUM1 and adds it to R0. The second Add instruction adds 4 to the contents of the pointer R2, so that it will contain the address value NUM2 when the above instruction is executed in the second pass through the loop. INDEXING AND ARRAYS A different kind of flexibility for accessing operands is useful in dealing with lists and arrays. Index Addressing mode The operation is indicated as X(Ri) where X=the constant value which defines an offset(also called a displacement). Ri=the name of the index register which contains address of a new location. The effective-address of the operand is given byEA=X+[Ri] The contents of the index-register are not changed in the process of generating the effective- address. The constant X may be given either → as an explicit number or → as a symbolic-name representing a numerical value. Fig(a) illustrates two ways of using the Index mode. In fig(a), the index register, R1, contains theaddress of a memory-location, and the value X defines an offset(also called a displacement) from thisaddress to the location where the operand isfound. To find EA of operand: Eg: Add 20(R1), R2 EA=>1000+20=1020 An alternative use is illustrated in fig(b). Here, the constant X corresponds to a memory address, and the contents of the index register define the offset to the operand. In either case, the effective-address is the sum of two values; one is given explicitly in the instruction, and the other is stored in a register. 22 Base with Index Addressing Mode Another version of the Index mode uses 2 registers which can be denoted as (Ri,Rj) Here, a second register may be used to contain the offset X. The second register is usually called the base register. The effective-address of the operand is given by EA=[Ri]+[Rj] This form of indexed addressing provides more flexibility in accessing operands because both components of the effective-address can be changed. Base with Index & Offset Addressing Mode Another version of the Index mode uses 2 registers plus a constant, which can be denoted as X(Ri,Rj) The effective-address of the operand is given by EA=X+[Ri]+[Rj] This added flexibility is useful in accessing multiple components inside each item in a record, where the beginning of an item is specified by the (Ri, Rj) part of the addressing-mode. In other words, this mode implements a 3-dimensionalarray. RELATIVE Addressing MODE This is similar to index-mode with one difference: The effective-address is determined using the PC in place of the general purpose register Ri. The operation is indicated as X(PC). X(PC) denotes an effective-address of the operand which is X locations above or below the current contents of PC. Since the addressed-location is identified "relative" to the PC, the name Relative mode is associated with this type of addressing. This mode is used commonly in conditional branch instructions. An instruction such as Branch >0LOOP ;Causes program execution to go to the branch target location identified by name LOOP if branch condition is satisfied. 23 ADDITIONAL ADDRESSING MODES 1) Auto Increment Addressing Mode  Effective-address of operand is contents of a register specified in the instruction (Fig:2.16).  After accessing the operand, the contents of this register are automatically incremented to point to the next item in a list.  Implicitly, the increment amount is1.  This mode is denoted as (Ri)+ ;whereRi=pointer-register. 2) Auto Decrement Addressing Mode  The contents of a register specified in the instruction are first automatically decremented andare then used as the effective-address of theoperand.  This mode is denoted as -(Ri) ;whereRi=pointer-register.  These2modescanbeusedtogethertoimplementanimportantdatastructurecalledastack. 24 25