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MIT School of Computing Department of Computer Science & Engineering SECOND Year Engineering -Processor Architecture and Interfacing Class - S.Y (SEM-I), PL Unit – III 80386DMicroprocessor AY 2024-2025 SEM-I Dr.Suva...

MIT School of Computing Department of Computer Science & Engineering SECOND Year Engineering -Processor Architecture and Interfacing Class - S.Y (SEM-I), PL Unit – III 80386DMicroprocessor AY 2024-2025 SEM-I Dr.Suvarna Joshi 1  MIT School of Computing Department of Computer Science & Engineering Unit-3 6 Hours 80386: Difference between 8086 & 80386. 80386 – Features, architecture, Register Set, 80386 Real mode segmentation PL and Address translation & D Addressing modes, Real Mode Instruction set of 80386, Pin Description of 80386. Dr.Suvarna Joshi 2 Dr.Suvarna Joshi 3  MIT School of Computing Department of Computer Science & Engineering 80386 Features (1) Introduced in 1985 by Intel Corporation. (2) 32 bit Address bus 32-bit 32 bit Data bus (3) Addressing capacity- 4G bytes (4) Operating frequency of 20-33 MHz PL. D (5) 132 Pins. (6) Intel’s first practical microprocessor to contain a 32-bit data bus and 32-bit memory address (7) higher clocking speeds and included a memory management unit. Dr.Suvarna Joshi 4  MIT School of Computing Department of Computer Science & Engineering 80386 Features (8) Improved efficiency (9) Instruction set, memory management compatible with 8086, 8088, and 80286 Microprocessor. PL (10) Can operates in real, protected D & virtual Mode. (11) Introduced paging, virtual memory concept. (12) Based on CMOS Technology. (13) Contains near about 2,75,000 Transistors. Dr.Suvarna Joshi 5  80386 Features 14) Can operate at 11.4 MIPS. 15) 11 Addressing modes. 16) Pipelined architecture Dr.Suvarna Joshi 6  Versions of 80386 Microprocessor 80386 DX 80386 SX (1) Address Bus is of 32 Bit. (1) Address Bus is of 24 Bit. (2) Data Bus is of 32 Bit. (2) Data Bus is of 16 Bit. (3) Total 132 Pins. (3)Total 100 Pins. (4) Can address upto (4)Can address upto Dr.Suvarna Joshi 7 MIT School of Computing Department of Computer Science & Engineering 80386 Architecture PL D Dr.Suvarna Joshi 8  MIT School of Computing Department of Computer Science & Engineering 80386 Architecture The Internal Architecture of 80386 is divided into 3 sections. Central Processing Unit Execution Unit PL D Instruction Unit Memory management unit Segmentation Paging Unit Bus interface unit Dr.Suvarna Joshi 9  MIT School of Computing Department of Computer Science & Engineering Central Processing Unit  The execution unit consists of the eight 32 bit general purpose registers (GPR)  64- bit barrel shifter PL D Dr.Suvarna Joshi 10 Consists of three subunits : control, data and protection test unit I) Control Unit:  contains microcode and special hardware allows processor. II) Data Unit:  Responsible for data operations  contains ALU, eight 32 bit general purpose registers and 64 bit barrel shifter. III)Protection Test Unit:  checks for segmentation violations Dr.Suvarna Joshi 11  MIT School of Computing Department of Computer Science & Engineering Central Processing Unit  Instruction unit Instruction decoding Passing to control unit Use of Barrel shifter PL Faster Multiplication opearion D Dr.Suvarna Joshi 12  MIT School of Computing Department of Computer Science & Engineering Memory Management Unit (MMU)  Two sub unit i.e. Segmentation Unit and Paging Unit.  Use of two address components, viz. segment and offset PL D  Maximum size of segments 4Gbytes  4 level Protection mechanism for segments Dr.Suvarna Joshi 13 The Paging unit  Memory organizations in terms of pages  works under the control of the segmentation unit  Segments and pages  Linear to Physical address conversion  limit and attribute PLA  control and attribute PLA Dr.Suvarna Joshi 14  MIT School of Computing Department of Computer Science & Engineering The 80386 has three modes of operation: 1. Real Address Mode (Real Mode) 2. Protected Virtual Addressing mode (Protected Mode) 3. Virtual 8086 mode. Bus Control Unit: PL D Communication with the outsideworld. full 32 bit bi-directional data and32-bit address bus. Dr.Suvarna Joshi 15  Processing of code fetch and data transfers  Address ,Data ,Control signal transfer for communication  Controlling external memory interface  address relocation facility  address pipelining  data bus sizing  Direct Byte Enable signals Dr.Suvarna Joshi 16 Instruction Prefetch Unit Instruction Prefetching 16 Byte Queue Dr.Suvarna Joshi 17  MIT School of Computing Department of Computer Science & Engineering Register Organization Of 80386 PL D Dr.Suvarna Joshi 18 Dr.Suvarna Joshi 19  MIT School of Computing Department of Computer Science & Engineering Register Organization Of 80386 eight 32 - bit general purpose registers extended register-E. Example : EAX,EBX PL etc. D EBP,ESP,ESI and EDI. CS and SS DS, ES, FS, GS are 4 data segment registers. Dr.Suvarna Joshi 20  1 MB address space in real mode..  Six simultaneously accessible memory blocks called segments.  Segments are addressed by 16-bit registers : CS, DS, ES, SS, FS and GS. A segment represents an independently accessible block of memory consisting of 64 K consecutive byte-wide storage locations Dr.Suvarna Joshi 21 Dr.Suvarna Joshi 22  MIT School of Computing Department of Computer Science & Engineering Flag Register of 80386 PL D Dr.Suvarna Joshi 23  MIT School of Computing Department of Computer Science & Engineering Flag Register  32 bit register.  Intel has reserved bits D18 to D31, D5 and D3, while D1 is always set at 1.  Two extra new flags VM and RFPLflags. D  IOPL (Input Output Privilege Level) flags  VM Virtual 8086 mode flag:- When it is set, the x86 processor is basically converted into a high-speed 8086 processor. if VM=1 virtual 8086 mode within the protection mode. set only for protected mode. Dr.Suvarna Joshi 24  MIT School of Computing Department of Computer Science & Engineering Flag Register RF:-Resume Flag  used with the debug register break points.  checked at the starting ofPLevery instruction cycle D  automatically reset after successful execution of every instruction, except for IRET and POPF instructions.  Usage of JMP, CALL and INT instructions for setting flag Dr.Suvarna Joshi 25 NT (Nested flag) : one system task invokes another task.(i.e. nested task). Dr.Suvarna Joshi 26  MIT School of Computing Department of Computer Science & Engineering Segment Descriptor Registers ⮚ not available for programmers ⮚ used to store the descriptor information, ⮚ six segment registers with corresponding PL descriptor registers. D Dr.Suvarna Joshi 27 Control Registers:  Three 32 bit control registers CR0, CR2 and CR3  Load and store instructions for access Dr.Suvarna Joshi 28  MIT School of Computing System Address Registers: Department of Computer Science & Engineering System Address Registers The 80386 supports four types of descriptor table, viz. (1) Global Descriptor Table PL (GDT), D (2) Interrupt Descriptor Table (IDT), (3) Local Descriptor Table (LDT), (4) Task State Segment Descriptor (TSS). They holds the addresses of corresponding segments. Dr.Suvarna Joshi 29 Associated with protected mode of 80386. Task reg(TR): Points to Task State Table Global Descriptor Table Reg(GDTR): points to Global Descriptor table Interrupt Descriptor table Reg(IDTR): It points to the Interrupt Descriptor table Local Descriptor table Reg(LDTR):It points to the local descriptor table. Dr.Suvarna Joshi 30 MIT School of Computing Department of Computer Science & Engineering Debug and Test Registers PL D Dr.Suvarna Joshi 31  MIT School of Computing System Address Registers: Department of Computer Science & Engineering Debug and Test Registers a set of 8 debug registers for hardware debugging. two registers DR4 and DR5 are Intel reserved. DR0 to DR3 used to store four program controllable breakpoint addresses PL DR6 and DR7 respectively D hold breakpoint status and breakpoint control information. Two more test register are provided by 80386 for page caching namely test control and test status register Dr.Suvarna Joshi 32  MIT School of Computing System Address Register Department of Computer Science & Engineering Real Address Mode of 80386  After reset, starts from memory location  works as a faster 8086  Default operand size 16 bit  The segment size -64K. PL  Overlapped or non-overlappedD segments.  read, write or execution operation for segments  no protection is available. Dr.Suvarna Joshi 33  MIT School of Computing System Address Register Department of Computer Science & Engineering Real Mode programming model of 80386 PL D Dr.Suvarna Joshi 34 Memory Addressing in Real Mode:  1Mbytes of physical memory  Paging unit disabled  Address generation is same manner like 8086  no protection is available.  64KB segments  Use of segment registers  Linear Address = Physical Address Dr.Suvarna Joshi 35  Six segments active at a time  Generation of protection fault If the EA exceeds 64KB,.  Segment overlapping  Program relocation.  A relocatable program is a program that can be placed in any area of the memory and executed without any change  Allows both programs and data to be relocated. Dr.Suvarna Joshi 36 Dr.Suvarna Joshi 37  MIT School of Computing System Address Register Department of Computer Science & Engineering Real Address Mode of 80386 PL D Dr.Suvarna Joshi 38  MIT School of Computing System Address Register Department of Computer Science & Engineering Protected Mode of 80386  All the capabilities of 80386 can be utilized in protected mode of operation.  4GB of physical memory  64TB of virtual memory address space. PL  use of additional instructions D  addressing modes Dr.Suvarna Joshi 39  Addressing in protected mode: The contents of segment registers are used as selectors to address descriptors which contain the segment limit and base address of the segment. The effective address (offset) is added with segment base address to calculate linear address. Dr.Suvarna Joshi 40 Dr.Suvarna Joshi 41  MIT School of Computing System Address Register Department of Computer Science & Engineering Protected Mode of 80386 PL D Dr.Suvarna Joshi 42  MIT School of Computing Department of Computer Science & Engineering Paging  memory management technique  Segments Organization in terms of pages  used for virtual memory multitasking operating system. PL  Paging divides the memory D into a fixed size pages.  pages do not have any logical relation with the program. Dr.Suvarna Joshi 43  MIT School of Computing Department of Computer Science & Engineering Paging  complete segment of a task need not be in the physical memory at any time.  Needs Only a few pages of the segments currently required in physical memory.  Reduction in task memory requirement of the task  Fetching of other pages of task as per requirement for execution, PL  Effective technique to manage theDphysical memory for multitasking systems. Dr.Suvarna Joshi 44  MIT School of Computing Department of Computer Science & Engineering Paging Unit:  converts the complete map of a task into 4k size pages,  Handling of task in terms of segments The task is further handled in terms of its page, rather than segments.  page directory, page tables and page.  uses a two level table mechanismPL  to convert a linear address Dprovided by segmentation unit into physical addresses Dr.Suvarna Joshi 45  MIT School of Computing Department of Computer Science & Engineering Page Directory:  4Kbytes in size.  4 bytes directory entry  Total of 1024 entries  Use of upper 10 bits of thePLlinear address as an index. D  The page directory entries point to page tables. Dr.Suvarna Joshi 46  MIT School of Computing Department of Computer Science & Engineering Page Table:  Each page table is of 4Kbytes in size and many contain a maximum of 1024 entries.  The page table entries contain the starting address of the page and the statistical information about the page.  The upper 20 bit page frame address PL is combined with the lower 12 bit of the linear address. D  The accessed bit A is set by 80386 before any access to the page. If A=1, the page is accessed, else unaccessed.  The D bit ( Dirty bit) is set before a write operation to the page is carried out.  The OS reserved bits are defined by the operating system software.  The User / Supervisor (U/S) bit and read/write bit are used to provide protection Dr.Suvarna Joshi 47 MIT School of Computing Department of Computer Science & Engineering PL D Dr.Suvarna Joshi 48 Addressing Modes of 80386 Dr.Suvarna Joshi 49 Addressing Modes of 386 Definition of Addressing Modes Addressing Modes: a method of specifying an operand Operands : in REG, Memory, I/O ports, and within Instruction * Control Transfer : direct, indirect addressing the modes available register addressing : REG immediate addressing: within Instruction direct addressing register indirect addressing MEM or I/O based addressing indexed addressing based indexed addressing Dr.Suvarna Joshi 50  Addressing Modes Register Addressing Mode can be accessed in byte, word, or double word sizes. MOV EAX, EBX Byte: AL, AH, BL, BH, CL, CH, DL, DH Word: AX, BX, CX, DX, SP, BP, SI, DI, CS, DS, SS, ES, FS, GS Double Word: EAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI Immediate Operand Addressing an operand is part of the instruction MOV AL, 15H 8 bits, 16 bits, and 32 bits in length Dr.Suvarna Joshi 51  Memory Addressing Modes Memory operands must be transferred to and from the CPU over the bus EFFECTIVE ADDRESS:  The offset calculated for a memory operand is called as EA.  It is an unsigned 32 bit no. that expresses the operand’s distance in bytes from the beginning of the segment in which it resides.  EA is calculated by adding any 4 combination of the components Dr.Suvarna Joshi 52  Displacement: 8 or 32 bit immediate data following the instruction.  16 bit displacement can be used by inserting an address prefix before instruction. Base:  contents of any general purpose register can be used as base. Index:  contents of any general purpose register can be used as index.  ESP can not be used as an index register Scale:  The index register’s contents can be multiplied (scaled) by a factor of 1,2,4 or 8  Scaled index mode is efficient for accessing arrays or structures Dr.Suvarna Joshi 53 EA = Base Register + (Index Register * Scaling Factor) + Displacement PA = Segment : Offset PA = Segment Register : EA  EAX  CS      SS   EBX  1     ECX    2   DS      PA   :  EDX     8,16 or 32 - bit displaceme nt ES   EBP  4 FS     8     ESI   GS       EDI   Dr.Suvarna Joshi 54 Different memory addressing modes are: Direct Addressing Register Indirect Addressing Based Addressing Indexed Addressing Scaled Indexed Addressing Based Indexed Addressing Based Scaled Indexed Addressing Based Index mode with displacement Based Scaled mode with displacement Dr.Suvarna Joshi 55  Direct Addressing Mode EA is taken from the displacement field of the instruction. EA is used as 8,16 or 32 bit displacement from the current value of the data segment register PA = Segment Base : Direct Address MOV CX, [1234H] EA = 1234H PA = DS + 1234H Dr.Suvarna Joshi 56 Register Indirect Addressing Mode EA = { base reg}/{index reg} PA = Segment Base : Offset PA = Segment Base :EA {EA= ECX} example : MOV EBX, [ECX] {PA= DS + ECX} EAX   EAX CS  EBX  EBX  SS  ECX        ECX  DS   EDX    PA  : OREDX  ES  ESP  EBP  FS  EBP        ESI  GS    ESI  EDI  EDI     Dr.Suvarna  Joshi 57  Based Addressing Mode Contents of a base register are added to displacement, in order to obtain the operand’s EA EA = {base register} + {8,16 or 32 bit displacement} E.g : MOV ESI,[EBX+23H] ; EA= EBX+23HEAX CS  EBX  PA= DSSS +ECX EA     DS EDX  8,16 or 32  bit displaceme nt  PA   :    ES    ESP    FS  EBP      GS  ESI  EDI   Dr.Suvarna Joshi 58  Indexed Addressing Mode Contents of a index register are added to displacement, in order to obtain the operand’s EA EA = {index register} + {8,16 or 32 bit displacement} E.g : SUB COUNT [EDI],EAX ; EA= EDI+Offset COUNT PA= DS + EA EAX   CS  EBX  SS  ECX      DS EDX  8,16 or 32  bit displaceme nt  PA   :    ES    ESP    FS  EBP      GS  ESI  EDI    Dr.Suvarna Joshi 59  Scaled Indexed Addressing Mode Contents of a index register are Multiplied by a scaling factor which is then added to displacement, in order to obtain the operand’s EA EA = {index register * Scaling factor} + {8,16 or 32 bit displacement} E.g : MOV [ESI*8],ECX  EAX  CS      SS    EBX  1     ECX   DS      2  PA   :  EDX     8,16 or 32 - bit displaceme nt ES   EBP  4 FS     8     ESI   GS        EDI   Dr.Suvarna Joshi 60  Based Indexed Addressing Mode Contents of a base register are added to the contents of index register to compute the operand’s EA EA = {base register} + {index register} E.g : MOV ESI,[ECX][EBX] ; EA= ECX+EBX PA= DS + EA Dr.Suvarna Joshi 61  Based Scaled Indexed Addressing Mode Contents of a index register are Multiplied by a scaling factor which is then added to base register, in order to obtain the operand’s EA EA = {index register * Scaling factor} + {base register} E.g : MOV ECX,[EDI * 4] [EBP] Dr.Suvarna Joshi 62 Based Indexed Addressing Mode with displacement Contents of a base register are added to the contents of index register with displacement to compute the operand’s EA EA = {base register} + {index register} + {8,16 or 32 bit displacement} E.g : MOV [EBX] [EBP+12345678H],EDI EA= EBX+EBP+12345678H PA= DS + EA Dr.Suvarna Joshi 63 Based Scaled Indexed Addressing Mode with displacement Contents of a index register are Multiplied by a scaling factor which is then added to base register with displacement, in order to obtain the operand’s EA EA = {index register * Scaling factor} + {base register} + {8,16 or 32 bit displacement} E.g : MOV [EBX * 8][ECX+ 5678H], ECX Dr.Suvarna Joshi 64  Pin Diagram Of 80386 A0 and A1 are encoded in Bus Enable to select any or all 4 bytes in a 32 bit wide mem. location Select the access of byte,word or double word of data.internally generated by A0 and A1 Executing s/w from mem location FFFFFFF0H , reset to real mode. 0mp is halted or executes interrupt acknowledge cycle WAIT /FWAIT Issued valid mem. I/O add Used for pipelining the address Dr.Suvarna Joshi 65  80386 Pin Descriptions W/R#: The write / read output distinguishes the write and read cycles from one another. D/C#: This data / control output pin distinguishes between a data transfer cycle from a machine control cycle like interrupt acknowledge. M/IO#: This output pin differentiates between the memory and I/O cycles. LOCK#: The LOCK# output pin enables the CPU to prevent the other bus masters from gaining the control of the system bus. NA#: The next address input pin, if activated, allows address pipelining, during 80386 bus cycles. Dr.Suvarna Joshi 66  80386 Pin Descriptions ADS#: The address status output pin indicates that the address bus and bus cycle definition pins( W/R#, D/C#, M/IO#, BE0# to BE3# ) are carrying the respective valid signals. The 80386 does not have any ALE signals and so this signals may be used for latching the address to external latches. READY#: The ready signals indicates to the CPU that the previous bus cycle has been terminated and the bus is ready for the next cycle. The signal is used to insert WAIT states in a bus cycle and is useful for interfacing of slow devices with CPU. VCC: These are system power supply lines. VSS: These return lines for the power supply. Dr.Suvarna Joshi 67  80386 Pin Descriptions BS16#: The bus size – 16 input pin allows the interfacing of 16 bit devices with the 32 bit wide 80386 data bus. Successive 16 bit bus cycles may be executed to read a 32 bit data from a peripheral. HOLD: The bus hold input pin enables the other bus masters to gain control of the system bus if it is asserted. HLDA: The bus hold acknowledge output indicates that a valid bus hold request has been received and the bus has been relinquished by the CPU. BUSY#: The busy input signal indicates to the CPU that the coprocessor is busy with the allocated task. Dr.Suvarna Joshi 68  ERROR#: The error input pin indicates to the CPU that the coprocessor has encountered an error while executing its instruction. PEREQ: The processor extension request output signal indicates to the CPU to fetch a data word for the coprocessor. INTR: This interrupt pin is a maskable interrupt, that can be masked using the IF of the flag register. NMI: A valid request signal at the non-maskable interrupt request input pin internally generates a non- maskable interrupt of type2 Dr.Suvarna Joshi 69  RESET: A high at this input pin suspends the current operation and restart the execution from the starting location. N / C : No connection pins are expected to be left open while connecting the 80386 in the circuit. Dr.Suvarna Joshi 70 Instruction set of 80386 Dr.Suvarna Joshi 71  80386 is compatible with 8086/80186/80286 processor Its instruction set includes all the 8086/80186/80286 instructions. These instructions can operate on 32 bit data words and 32 bit offsets. It includes of several new instructions. Dr.Suvarna Joshi 72 BIT SCAN AND TEST INSTRUCTIONS BT BTS BTR BTC BSF BSR Dr.Suvarna Joshi 73 DATA TYPE CONVERSIONS CWDE CDQ Dr.Suvarna Joshi 74  SEGMENT LOAD INSTRUCTIONS LFS LGS LSS Dr.Suvarna Joshi 75 MOVE AND EXPAND GROUP MOVSX MOVZX Dr.Suvarna Joshi 76 CONDITIONAL BYTE SET SETCC Dr.Suvarna Joshi 77 SHIFTS BETWEEN WORDS SHLD SHRD Dr.Suvarna Joshi 78 BIT SCAN AND TEST INSTRUCTIONS Dr.Suvarna Joshi 79  BT (BIT TEST) Mnemonic: BT Algorithm: CF=0 if bit =0 OR CF=1 if bit=1 Operation: This instruction tests the status of the specified bit in the instruction. The status of that bit is copied to the carry flag. E.g: BT EAX, 05H ; copies bit 5 of EAX to the carry flag Before Execution: EAX  00001111000011110000111100001111 CF1 After Execution: EAX  00001111000011110000111100001111 Dr.Suvarna Joshi 80 CF0 BTS (BIT TEST AND SET) Mnemonic: BTS Algorithm: CF=0 if bit =0 and bit=1 OR CF=1 if bit=1 Operation: This instruction tests the status of the specified bit in the instruction. The status of that bit is copied to the carry flag. Then the bit is SET. E.g: BTS EAX, 05H ; copies bit 5 of EAX to the carry flag and then bit 5 of EAX is SET Before Execution: EAX  0000 1111 0000 1111 0000 1111 0000 1111 CF1 After Execution: EAX  0000 1111 0000 1111 0000 1111 0001 1111 CF0 Dr.Suvarna Joshi 81  BTS (BIT TEST AND Mnemonic: BTRRESET) Algorithm: CF=0 if bit =0 OR CF=1 if bit=1 and bit=0 Operation: This instruction tests the status of the specified bit in the instruction. The status of that bit is copied to the carry flag. Then the bit is RESET E.g: BTR EAX, 05H ; copies bit 5 of EAX to the carry flag and then bit 5 of EAX is RESET Before Execution: EAX  0000 1111 0000 1111 0000 1111 0001 1111 CF0 After Execution: EAX  0000 1111 0000 1111 0000 1111 0000 1111 CF1 Dr.Suvarna Joshi 82 BTC (BIT TEST AND COMPLEMENT) Mnemonic: BTC Algorithm: CF=0 if bit =0 then bit=1OR CF=1 if bit=1 then bit=0 Operation: This instruction tests the status of the specified bit in the instruction. The status of that bit is copied to the carry flag. The bit is complemented E.g: BTC EAX, 05H ; copies bit 5 of EAX to the carry flag Before Execution: EAX  0000 1111 0000 1111 0000 1111 0000 1111 CF1 After Execution: EAX  0000 1111 0000 1111 0000 1111 0001 1111 CF0 Dr.Suvarna Joshi 83 DATA TYPE CONVERSIONS Dr.Suvarna Joshi 84 CWDE(CONVERT WORD TO DOUBLE WORD) Mnemonic: CWDE Algorithm: If MSB of AX =1 then EAX =FFFFFFFFH else EAX= 00000000H Operation: This instruction copies the sign bit of AX to all the bits of the EAX register. E.g: AX= 0F0FH CWDE Before Execution: EAX  0000 1111 0000 1111 0000 1111 0000 1111 After Execution: EAX  0000 0000 0000 0000 0000 1111 0000 1111 Dr.Suvarna Joshi 85 CDQ(CONVERT WORD TO QUAD WORD) Mnemonic: CDQ Algorithm: If MSB of EAX =1 then EDX =FFFFFFFFH else EDX= 00000000H Operation: This instruction copies the sign bit of EAX to all the bits in the EDX register. E.g: EAX=0F0F 0F0FH CDQ Before Execution: EAX  0000 1111 0000 1111 0000 1111 0000 1111 EDX 0000 1111 0000 1111 0000 1111 0000 1111 After Execution: EAX  0000 1111 0000 1111 0000 1111 0001 1111 EDX 0000 0000 0000 0000 0000 0000 0000 0000 Dr.Suvarna Joshi 86 SEGMENT LOAD INSTRUCTIONS These instructions manipulate the addresses of the variables, rather than the contents or values of the variables. They are mainly used for list processing based variables and string instructions. Dr.Suvarna Joshi 87  LFS(LOAD POINTER WITH FS) LOAD REGISTER AND FS WITH WORDS FROM THE MEMORY Mnemonic: LFS register, source Algorithm: Register= First word, FS= second word Operation: Register source, FS(source+2) This instruction is a 2 byte. FS is used as segment register for memory. This instruction copies a word from two memory locations into register specified in the instruction. It then copies a word from next two memory locations in to the FS register. E.g: LFS BX,; this instruction copies a word from Mem locations at an offset of 1100H and 1101H into the BX reg and copies a word from next two mem locations with the offset of 1102H and 1103H in to the FS register Dr.Suvarna Joshi 88  GS 1100 23 1101 24 1102 12 LGS CX,; 1103 11 Before execution CX=2300H After execution CL=23 CH=24 GS =1112 Dr.Suvarna Joshi 89  LGS(LOAD POINTER WITH GS) OAD REGISTER AND GS WITH WORDS FROM THE MEMORY Mnemonic: LGS register, source Algorithm: Register= First word, GS= second word Operation: Register source, GS(source+2) This instruction is a 2 byte. GS is used as segment register for memory. This instruction copies a word from two memory locations into register specified in the instruction. It then copies a word from next two memory locations in to the GS register. E.g: LGS BX,; this instruction copies a word from mem locations at an offset of 1100H and 1101H into the BX reg and copies a word from next two mem locations with the offset of 1102H and 1103H in to the GS register Dr.Suvarna Joshi 90  LSS(LOAD POINTER WITH SS) AD REGISTER AND SS WITH WORDS FROM THE MEMORY Mnemonic: LSS register, source Algorithm: Register= First word, SS= second word Operation: Register source, SS(source+2) This instruction is a 2 byte. SS is used as segment register for memory. This instruction copies a word from two memory locations into register specified in the instruction. It then copies a word from next two memory locations in to the SS register. E.g: LSS BX,; this instruction copies a word from mem locations at an offset of 1100H and 1101H into the BX reg and copies a word from next two mem locations with the offset of 1102H and 1103H in to the SS register Dr.Suvarna Joshi 91 MOVE AND EXPAND GROUP Dr.Suvarna Joshi 92  MOVSX (MOVE BYTE OR WORD OR DOUBLE WORD WITH SIGN EXTENSION ) Mnemonic: MOVSX destination, source Algorithm: Destination = Source Operation: Destination  Source The source can be a byte or word or double word of data in reg or memory. The destination can be either 16/32 bit register. If the source is 8 bit and destination is of 16 bit then the signed bit of MSB of the 8 bit no. is copied to the 16 bit no. If the source is 16 bit and destination is of 32 bit then the signed bit of MSB of the 16 bit no. is copied to the 32 bit no. E.g: MOVSX EBX,AX It copies a word from the AX register to the BX register. The signed bit of AX is copied to the MSB of the EBX register. Dr.Suvarna Joshi 93  MOVSX EBX,AX AX 1000 0111 1111 1110 BX 1000 0111 1111 1110 EBX 1111 1111 1111 1111 1000 0111 1111 1110 Dr.Suvarna Joshi 94  MOVZX (MOVE BYTE OR WORD OR DOUBLE WORD WITH ZERO EXTENDED ) Mnemonic: MOVSX destination, source Algorithm: Destination = Source Operation: Destination  Source The source can be a byte or word or double word of data in reg or memory. The destination can be either 16/32 bit register. If the source is 8 bit and destination is of 16 bit then zeros are copied to the 16 bit no. If the source is 16 bit and destination is of 32 bit then the zeros are copied to the 32 bit no. E.g: MOVZX EBX,AX It copies a word from the AX register to the BX register. The zeros are copied to the MSB of the EBX register. Dr.Suvarna Joshi 95  MOVZX EBX,AX AX 1000 0111 1111 1110 BX 1000 0111 1111 1110 EBX 0000 0000 0000 0000 1000 0111 1111 1110 Dr.Suvarna Joshi 96  SHLD( SHIFT LEFT DOUBLE ) Mnemonic: SHLD destination, source,count Algorithm: Shift left from one operand to another. Operation: This instruction is used to shift specified no. of bits left from one operand to another. E.g: SHLD EAX,ECX,3 ; this instruction shifts the upper 3 bits from ECX in to the lower 3 bits of EAX register Dr.Suvarna Joshi 97  SHLD EAX,ECX,3 this instruction shifts the upper 3 bits from ECX in to the lower 3 bits of EAX register EAX 1111 1000 1000 1000 0000 1001 1100 1111 ECX 0001 1111 1111 1111 1111 1110 0000 0000 After execution EAX 1111 1000 1000 1000 0000 1001 1100 1000 EAX--ECX Dr.Suvarna Joshi 98 SHRD( SHIFT RIGHT DOUBLESHRD Mnemonic: ) destination, source,count Algorithm: Shift right from one operand to another. Operation: This instruction is used to shift specified no. of bits right from one operand to another. E.g: SHRD EAX,ECX,3 ; this instruction shifts the lower 3 bits from ECX in to the upper 3 bits of EAX register Dr.Suvarna Joshi 99 SHRD EAX,ECX,4 ; this instruction shifts the lower 4 bits from ECX in to the upper 4 bits of EAX register EAX 1111 1000 1000 1000 0000 1001 1100 1111 ECX 1100 1111 0000 1010 0101 1100 1001 1000 After exe. EAX 1000 1000 1000 1000 0000 1001 1100 1111 Dr.Suvarna Joshi 100