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Questions and Answers
What is the purpose of a scaling factor in index registers?
What is the purpose of a scaling factor in index registers?
- To multiply the index register contents for efficient array access (correct)
- To convert the index register into a base register
- To determine the type of data stored in memory
- To increase the size of the memory address
Which memory addressing mode uses the displacement field directly to calculate the effective address?
Which memory addressing mode uses the displacement field directly to calculate the effective address?
- Based Indexed Addressing
- Register Indirect Addressing
- Direct Addressing Mode (correct)
- Scaled Indexed Addressing
Which of the following addressing modes is NOT mentioned in the content?
Which of the following addressing modes is NOT mentioned in the content?
- Based Addressing
- Based Index mode with displacement
- Indirect Addressing (correct)
- Based Scaled Indexed Addressing
Which equation correctly describes the relationship between effective address and physical address?
Which equation correctly describes the relationship between effective address and physical address?
What is an invalid use of the ESP register according to the content?
What is an invalid use of the ESP register according to the content?
What does the Global Descriptor Table Register (GDTR) point to?
What does the Global Descriptor Table Register (GDTR) point to?
Which of the following registers are utilized for hardware debugging in the 80386?
Which of the following registers are utilized for hardware debugging in the 80386?
In Real Address Mode of 80386, what is the default operand size?
In Real Address Mode of 80386, what is the default operand size?
Which statement best describes the memory addressing in Real Mode for the 80386?
Which statement best describes the memory addressing in Real Mode for the 80386?
Which of the following is true regarding the memory segments in Real Address Mode?
Which of the following is true regarding the memory segments in Real Address Mode?
What is the purpose of the Task State Segment Descriptor (TSS)?
What is the purpose of the Task State Segment Descriptor (TSS)?
Which descriptor table is associated with handling interrupts in the 80386?
Which descriptor table is associated with handling interrupts in the 80386?
What role does the Local Descriptor Table Register (LDTR) serve in the 80386 architecture?
What role does the Local Descriptor Table Register (LDTR) serve in the 80386 architecture?
What is the primary function of the memory management unit introduced in the 80386?
What is the primary function of the memory management unit introduced in the 80386?
Which of the following features distinguishes the 80386 from its predecessors like the 8086?
Which of the following features distinguishes the 80386 from its predecessors like the 8086?
What operating modes does the 80386 microprocessor support?
What operating modes does the 80386 microprocessor support?
What is the addressing capacity of the 80386?
What is the addressing capacity of the 80386?
Which version of the 80386 features a 24-bit address bus?
Which version of the 80386 features a 24-bit address bus?
How many addressing modes does the 80386 support?
How many addressing modes does the 80386 support?
What technological advancement is the 80386 based on?
What technological advancement is the 80386 based on?
What is the maximum operational speed of the 80386?
What is the maximum operational speed of the 80386?
What happens to the most significant bits (MSB) when copying from a source of 8 bits to a destination of 16 bits?
What happens to the most significant bits (MSB) when copying from a source of 8 bits to a destination of 16 bits?
Which instruction shifts specified bits from one operand to another in a left direction?
Which instruction shifts specified bits from one operand to another in a left direction?
What is the purpose of the SHRD instruction?
What is the purpose of the SHRD instruction?
If the instruction SHLD EAX, ECX, 3 is executed, which bits from ECX are affected in the EAX register?
If the instruction SHLD EAX, ECX, 3 is executed, which bits from ECX are affected in the EAX register?
What occurs after executing the instruction MOVZX EBX, AX?
What occurs after executing the instruction MOVZX EBX, AX?
What does the operand 'count' specify in the SHLD and SHRD instructions?
What does the operand 'count' specify in the SHLD and SHRD instructions?
After executing SHRD EAX, ECX, 4, how is EAX modified?
After executing SHRD EAX, ECX, 4, how is EAX modified?
What is the result in the EBX register after executing MOVZX EBX, AX if AX is 1000 0111 1111 1110?
What is the result in the EBX register after executing MOVZX EBX, AX if AX is 1000 0111 1111 1110?
What is the correct formula to calculate the Effective Address (EA) using base register and displacement?
What is the correct formula to calculate the Effective Address (EA) using base register and displacement?
In which addressing mode is the contents of an index register multiplied by a scaling factor?
In which addressing mode is the contents of an index register multiplied by a scaling factor?
Which addressing mode combines the contents of a base register and an index register to compute the Effective Address?
Which addressing mode combines the contents of a base register and an index register to compute the Effective Address?
Which expression is used to calculate the Physical Address (PA) in the case of effective addresses?
Which expression is used to calculate the Physical Address (PA) in the case of effective addresses?
What is the primary function of the displacement in addressing modes?
What is the primary function of the displacement in addressing modes?
Which example demonstrates the Indexed Addressing Mode?
Which example demonstrates the Indexed Addressing Mode?
In the Scaled Indexed Addressing Mode with displacement, what factors contribute to calculating the Effective Address?
In the Scaled Indexed Addressing Mode with displacement, what factors contribute to calculating the Effective Address?
Which mode uses both the base register and the index register along with displacement?
Which mode uses both the base register and the index register along with displacement?
What is the formula for the Effective Address in Based Scaled Indexed Addressing Mode?
What is the formula for the Effective Address in Based Scaled Indexed Addressing Mode?
In Register Indirect Addressing Mode, which register is commonly used to directly find the Effective Address?
In Register Indirect Addressing Mode, which register is commonly used to directly find the Effective Address?
What distinguishes Based Scaled Indexed Addressing Mode from standard Based Addressing Mode?
What distinguishes Based Scaled Indexed Addressing Mode from standard Based Addressing Mode?
Which of the following correctly represents the Effective Address in the Based Indexed Addressing Mode?
Which of the following correctly represents the Effective Address in the Based Indexed Addressing Mode?
What is the purpose of segment registers in addressing modes?
What is the purpose of segment registers in addressing modes?
When computing the Effective Address, which of the following aspects is NOT typically involved?
When computing the Effective Address, which of the following aspects is NOT typically involved?
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Study Notes
80386 Microprocessor
- 80386 was released in 1985 by Intel
- 32 bit address bus and 32 bit data bus
- 4 GB addressing capacity
- Clock speeds of 20 - 33 MHz
- 132 pins
- Included a memory management unit
- Compatible with 8086, 8088, and 80286 processors
- Operates in Real, Protected, and Virtual modes
- Introduced Paging and Virtual Memory
- CMOS technology
- Contains 275,000 transistors
- Operates at 11.4 MIPS
- 11 addressing modes
- Pipelined architecture
80386 Versions
- 80386 DX: 32 bit Address Bus, 32 bit Data Bus, 132 pins
- 80386 SX: 24 bit Address Bus, 16 bit Data Bus, 100 pins
Register Set
- Global Descriptor Table (GDT)
- Interrupt Descriptor Table (IDT)
- Local Descriptor Table (LDT)
- Task State Segment Descriptor (TSS)
- Task Register (TR)
- Global Descriptor Table Register (GDTR)
- Interrupt Descriptor Table Register (IDTR)
- Local Descriptor Table Register (LDTR)
Debug and Test Registers
- 8 debug registers. Used for hardware debugging.
- DR0 to DR3 store breakpoint adresses
- DR6 and DR7 store breakpoint status and control information
- 2 test registers for page caching: Test Control and Test Status Register
Real Mode of 80386
- Starts from memory location 0 after reset
- Operates as a faster version of the 8086
- Default operand size: 16 bit
- Segment size: 64 KB
- Overlapped or non-overlapped segments
- No protection is available
- ESP can not be used as an index register
Memory Addressing in Real Mode
- 1 MB of physical memory
- Paging unit is disabled
- Address generation is the same as the 8086
- No protection is available
Addressing Modes
- Direct Addressing: EA is taken from the displacement field of the instruction.
- Register Indirect Addressing: EA is taken from a base or index register.
- Based Addressing: EA is calculated by adding the contents of a base register to a displacement.
- Indexed Addressing: EA is calculated by adding the contents of an index register to a displacement.
- Scaled Indexed Addressing: EA is calculated by multiplying the contents of an index register by a scaling factor and adding the result to a displacement.
- Based Indexed Addressing: EA is calculated by adding the contents of a base register to the contents of an index register
- Based Scaled Indexed Addressing: EA is calculated by multiplying the contents of an index register by a scaling factor, adding the result to the contents of a base register.
- Based Index mode with displacement: EA is calculated by adding the contents of a base register to the contents of an index register and a displacement.
- Based Scaled mode with displacement: EA is calculated by multiplying the contents of an index register by a scaling factor, adding the result to the contents of a base register and a displacement.
80386 Pin Description
- A0 and A1 pins are encoded in Bus Enable to select any or all 4 bytes of a 32-bit wide memory
- The destination of data moves can be either 16 or 32 bit registers
- If the source is 8 bit and the destination is 16 bit, zeros are copied to the upper 8 bits of the destination
- If the source is 16 bit and the destination is 32 bit, zeros are copied to the upper 16 bits of the destination.
Instructions
- MOVZX: Copies a value from a smaller source register to a larger destination register, filling the unused bits with zeros.
- SHLD (SHIFT LEFT DOUBLE): Shift left from one operand to another. Shifts specified number of bits left from one operand to another.
- SHRD (SHIFT RIGHT DOUBLE): Shift right from one operand to another. Shifts specified number of bits right from one operand to another.
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