Computer Organization and Architecture: Processor Structure - PDF

+ William Stallings Computer Organization and Architecture 10th Edition © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Chapter 14 Processor Structure and Function © 2016 Pearson Education, Inc., Hoboken, N...

+ William Stallings Computer Organization and Architecture 10th Edition © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Chapter 14 Processor Structure and Function © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Processor Organization Processor Requirements: ◼ Fetch instruction ◼ The processor reads an instruction from memory (register, cache, main memory) ◼ Interpret instruction ◼ The instruction is decoded to determine what action is required ◼ Fetch data ◼ The execution of an instruction may require reading data from memory or an I/O module ◼ Process data ◼ The execution of an instruction may require performing some arithmetic or logical operation on data ◼ Write data ◼ The results of an execution may require writing data to memory or an I/O module ◼ In order to do these things the processor needs to store some data temporarily and therefore needs a small internal memory © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Registers ALU Control Unit Control Data Address Bus Bus Bus System Bus Figure 14.1 The CPU with the System Bus © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Arithmetic and Logic Unit Status Flags Registers Shifter Internal CPU Bus Complementer Arithmetic and Boolean Logic Control Unit Control Paths Figure 14.2 Internal Structure of the CPU © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Register Organization ◼ Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy ◼ The registers in the processor perform two roles: User-Visible Registers Control and Status Registers ◼ Enable the machine or ◼ Used by the control unit to assembly language control the operation of the programmer to minimize main processor and by privileged memory references by operating system programs to optimizing use of registers control the execution of programs © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  User-Visible Registers Categories: Referenced by means of General purpose the machine language Can be assigned to a variety of functions by the programmer that the processor Data executes May be used only to hold data and cannot be employed in the calculation of an operand address Address May be somewhat general purpose or may be devoted to a particular addressing mode Examples: segment pointers, index registers, stack pointer Condition codes Also referred to as flags Bits set by the processor hardware as the result of operations © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Table 14.1 Condition Codes Advantages Disadvantages 1. Because condition codes are set by normal 1. Condition codes add complexity, both to arithmetic and data movement instructions, the hardware and software. Condition code they should reduce the number of bits are often modified in different ways COMPARE and TEST instructions needed. by different instructions, making life more 2. Conditional instructions, such as BRANCH difficult for both the microprogrammer are simplified relative to composite and compiler writer. instructions, such as TEST AND 2. Condition codes are irregular; they are BRANCH. typically not part of the main data path, so 3. Condition codes facilitate multiway they require extra hardware connections. branches. For example, a TEST instruction 3. Often condition code machines must add can be followed by two branches, one on special non-condition-code instructions for less than or equal to zero and one on special situations anyway, such as bit greater than zero. checking, loop control, and atomic semaphore operations. 4. Condition codes can be saved on the stack 4. In a pipelined implementation, condition during subroutine calls along with other codes require special synchronization to register information. avoid conflicts. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Control and Status Registers Four registers are essential to instruction execution: ◼ Program counter (PC) ◼ Contains the address of an instruction to be fetched ◼ Instruction register (IR) ◼ Contains the instruction most recently fetched ◼ Memory address register (MAR) ◼ Contains the address of a location in memory ◼ Memory buffer register (MBR) ◼ Contains a word of data to be written to memory or the word most recently read © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Program Status Word (PSW) Register or set of registers that contain status information Common fields or flags include: Sign Zero Carry Equal Overflow Interrupt Enable/Disable Supervisor © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Data registers General registers General Registers D0 AX Accumulator EAX AX D1 BX Base EBX BX D2 CX Count ECX CX D3 DX Data EDX DX D4 D5 Pointers & index ESP SP D6 SP Stack ptr EBP BP D7 BP Base ptr ESI SI SI Source index EDI DI Address registers DI Dest index A0 Program Status A1 Segment FLAGS Register A2 CS Code Instruction Pointer A3 DS Data A4 SS Stack (c) 80386 - Pentium 4 A5 ES Extrat A6 A7´ Program status Flags Instr ptr Program status Program counter (b) 8086 Status register (a) MC68000 Figure 14.3 Example Microprocessor Register Organizations © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Includes the following stages: Instruction Cycle Fetch Execute Interrupt If interrupts are enabled Read the next and an interrupt has Interpret the opcode instruction from occurred, save the and perform the memory into the current process state indicated operation processor and service the interrupt © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Fetch Interrupt Indirect Execute Figure 14.4 The Instruction Cycle © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Indirection Indirection Instruction Operand Operand fetch fetch store Multiple Multiple operands results Instruction Instruction Operand Operand Data address operation address address Operation calculation decoding calculation calculation Instruction complete, Return for string fetch next instruction or vector data No interrupt Interrupt check Interrupt Interrupt Figure 14.5 Instruction Cycle State Diagram © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  CPU PC MAR Memory Control Unit IR MBR Address Data Control Bus Bus Bus MBR = Memory buffer register MAR = Memory address register IR = Instruction register PC = Program counter Figure 14.6 Data Flow, Fetch Cycle © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  CPU MAR Memory Control Unit MBR Address Data Control Bus Bus Bus Figure 14.7 Data Flow, Indirect Cycle © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  CPU PC MAR Memory Control Unit MBR Address Data Control Bus Bus Bus Figure 14.8 Data Flow, Interrupt Cycle © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Pipelining Strategy To apply this concept to instruction execution we must Similar to the use of recognize that an an assembly line in a instruction has a manufacturing plant number of stages New inputs are accepted at one end before previously accepted inputs appear as outputs at the other end © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Instruction Instruction Result Fetch Execute (a) Simplified view Wait New address Wait Instruction Instruction Result Fetch Execute Discard (b) Expanded view Figure 14.9 Two-Stage Instruction Pipeline © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Additional Stages ◼ Fetch instruction (FI) ◼ Read the next expected ◼ Fetch operands (FO) instruction into a buffer ◼ Fetch each operand from memory ◼ Decode instruction (DI) ◼ Operands in registers need ◼ Determine the opcode and not be fetched the operand specifiers ◼ Execute instruction (EI) ◼ Calculate operands (CO) ◼ Perform the indicated ◼ Calculate the effective operation and store the address of each source result, if any, in the specified operand destination operand location ◼ This may involve displacement, register ◼ Write operand (WO) indirect, indirect, or other ◼ Store the result in memory forms of address calculation © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Time 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Instruction 1 FI DI CO FO EI WO Instruction 2 FI DI CO FO EI WO Instruction 3 FI DI CO FO EI WO Instruction 4 FI DI CO FO EI WO Instruction 5 FI DI CO FO EI WO Instruction 6 FI DI CO FO EI WO Instruction 7 FI DI CO FO EI WO Instruction 8 FI DI CO FO EI WO Instruction 9 FI DI CO FO EI WO Figure 14.10 Timing Diagram for Instruction Pipeline Operation © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Time Branch Penalty 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Instruction 1 FI DI CO FO EI WO Instruction 2 FI DI CO FO EI WO Instruction 3 FI DI CO FO EI WO Instruction 4 FI DI CO FO Instruction 5 FI DI CO Instruction 6 FI DI Instruction 7 FI Instruction 15 FI DI CO FO EI WO Instruction 16 FI DI CO FO EI WO Figure 14.11 The Effect of a Conditional Branch on Instruction Pipeline Operation © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Fetch Instruction FI Decode DI Instruction Calculate CO Operands Yes Uncon- ditional Branch? No Fetch FO Operands Execute EI Instruction Update Write PC WO Operands Empty Pipe Yes Branch No or Inter -rupt? Figure 14.12 Six-Stage Instruction Pipeline © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  FI DI CO FO EI WO FI DI CO FO EI WO 1 I1 1 I1 2 I2 I1 2 I2 I1 3 I3 I2 I1 3 I3 I2 I1 4 I4 I3 I2 I1 4 I4 I3 I2 I1 5 I5 I4 I3 I2 I1 5 I5 I4 I3 I2 I1 6 I6 I5 I4 I3 I2 I1 6 I6 I5 I4 I3 I2 I1 Time 7 I7 I6 I5 I4 I3 I2 7 I7 I6 I5 I4 I3 I2 8 I8 I7 I6 I5 I4 I3 8 I15 I3 9 I9 I8 I7 I6 I5 I4 9 I16 I15 10 I9 I8 I7 I6 I5 10 I16 I15 11 I9 I8 I7 I6 11 I16 I15 12 I9 I8 I7 12 I16 I15 13 I9 I8 13 I16 I15 14 I9 14 I16 (a) No branches (b) With conditional branch Figure 14.13 An Alternative Pipeline Depiction © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  12 10 k = 12 stages Speedup factor 8 k = 9 stages 6 k = 6 stages 4 2 0 1 2 4 8 16 32 64 128 Number of instructions (log scale) (a) 14 12 n = 30 instructions 10 Speedup factor 8 n = 20 instructions 6 n = 10 instructions 4 2 0 0 5 10 15 20 Number of stages (b) Figure 14.14 Speedup Factors with Instruction Pipelining © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Pipeline Hazards Occur when the pipeline, or some portion of the There are three types pipeline, must stall of hazards: because conditions Resource do not permit Data continued execution Control Also referred to as a pipeline bubble © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Clock cycle 1 2 3 4 5 6 7 8 9 I1 FI DI FO EI WO Instrutcion I2 FI DI FO EI WO I3 FI DI FO EI WO I4 FI DI FO EI WO (a) Five-stage pipeline, ideal case Clock cycle 1 2 3 4 5 6 7 8 9 I1 FI DI FO EI WO Instrutcion I2 FI DI FO EI WO I3 Idle FI DI FO EI WO I4 FI DI FO EI WO (b) I1 source operand in memory Figure 14.15 Example of Resource Hazard © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Clock cycle 1 2 3 4 5 6 7 8 9 10 ADD EAX, EBX FI DI FO EI WO SUB ECX, EAX FI DI Idle FO EI WO I3 FI DI FO EI WO I4 FI DI FO EI WO Figure 14.16 Example of Data Hazard © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Types of Data Hazard ◼ Read after write (RAW), or true dependency ◼ An instruction modifies a register or memory location ◼ Succeeding instruction reads data in memory or register location ◼ Hazard occurs if the read takes place before write operation is complete ◼ Write after read (WAR), or antidependency ◼ An instruction reads a register or memory location ◼ Succeeding instruction writes to the location ◼ Hazard occurs if the write operation completes before the read operation takes place ◼ Write after write (WAW), or output dependency ◼ Two instructions both write to the same location ◼ Hazard occurs if the write operations take place in the reverse order of the intended sequence © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Control Hazard ◼ Also known as a branch hazard ◼ Occurs when the pipeline makes the wrong decision on a branch prediction ◼ Brings instructions into the pipeline that must subsequently be discarded ◼ Dealing with Branches: ◼ Multiple streams ◼ Prefetch branch target ◼ Loop buffer ◼ Branch prediction ◼ Delayed branch © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Multiple Streams A simple pipeline suffers a penalty for a branch instruction because it must choose one of two instructions to fetch next and may make the wrong choice A brute-force approach is to replicate the initial portions of the pipeline and allow the pipeline to fetch both instructions, making use of two streams Drawbacks: With multiple pipelines there are contention delays for access to the registers and to memory Additional branch instructions may enter the pipeline before the original branch decision is resolved © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Prefetch Branch Target ◼ When a conditional branch is recognized, the target of the branch is prefetched, in addition to the instruction following the branch ◼ Target is then saved until the branch instruction is executed ◼ If the branch is taken, the target has already been prefetched ◼ IBM 360/91 uses this approach + © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Loop Buffer ◼ Small, very-high speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions, in sequence ◼ Benefits: ◼ Instructions fetched in sequence will be available without the usual memory access time ◼ If a branch occurs to a target just a few locations ahead of the address of the branch instruction, the target will already be in the buffer ◼ This strategy is particularly well suited to dealing with loops ◼ Similar in principle to a cache dedicated to instructions ◼ Differences: ◼ The loop buffer only retains instructions in sequence ◼ Is much smaller in size and hence lower in cost © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Branch address Instruction to be 8 decoded in case of hit Loop Buffer (256 bytes) Most significant address bits compared to determine a hit Figure 14.17 Loop Buffer © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Branch Prediction ◼ Various techniques can be used to predict whether a branch will be taken: 1. Predict never taken ◼ These approaches are static 2. Predict always taken ◼ They do not depend on the execution history up to the time of 3. Predict by opcode the conditional branch instruction 1. Taken/not taken switch ◼ These approaches are dynamic 2. Branch history table ◼ They depend on the execution history © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Read next Read next conditional conditional branch instr branch instr Predict taken Predict not taken Yes Branch No Branch taken? taken? No Yes Read next Read next conditional conditional branch instr branch instr Predict taken Predict not taken Yes Branch No No Branch taken? taken? Yes Figure 14.18 Branch Prediction Flow Chart © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Not Taken Taken Predict Predict Taken Taken Taken Not Taken Taken Not Taken Predict Predict Not Taken Not Taken Not Taken Taken Figure 14.19 Branch Prediction State Diagram © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Next sequential address Select Memory E Branch Miss Handling (a) Predict never taken strategy Next sequential address IPFAR Branch instruction Target address address State Select Lookup Memory Add new IPFAR = instruction entry prefix address register Update state Branch Miss Redirect Handling E (b) Branch history table strategy Figure 14.20 Dealing with Branches © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Intel 80486 Pipelining Fetch Objective is to fill the prefetch buffers with new data as soon as Operates independently of the other stages to keep the prefetch the old data have been consumed by the instruction decoder buffers full Decode stage 1 All opcode and addressing-mode 3 bytes of instruction are passed to the D1 D1 decoder can then direct the D2 stage to information is decoded in the D1 stage stage from the prefetch buffers capture the rest of the instruction Decode stage 2 Also controls the computation of the more complex addressing Expands each opcode into control signals for the ALU modes Execute Stage includes ALU operations, cache access, and register update Write back Updates registers and status flags modified during the preceding execute stage © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Fetch D1 D2 EX WB MOV Reg1, Mem1 Fetch D1 D2 EX WB MOV Reg1, Reg2 Fetch D1 D2 EX WB MOV Mem2, Reg1 (a) No Data Load Delay in the Pipeline Fetch D1 D2 EX WB MOV Reg1, Mem1 Fetch D1 D2 EX MOV Reg2, (Reg1) (b) Pointer Load Delay Fetch D1 D2 EX WB CMP Reg1, Imm Fetch D1 D2 EX Jcc Target Fetch D1 D2 EX Target (c) Branch Instruction Timing Figure 14.21 80486 Instruction Pipeline Examples © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  (a) Integer Unit in 32-bit Mode Type Number Length (bits) Purpose General 8 32 General-purpose user registers Segment 6 16 Contain segment selectors EFLAGS 1 32 Status and control bits Instruction Pointer 1 32 Instruction pointer (b) Integer Unit in 64-bit Mode Table 14.2 Type Number Length (bits) Purpose General 16 32 General-purpose user registers Segment RFLAGS 6 1 16 64 Contain segment selectors Status and control bits x86 Processor Instruction Pointer 1 64 Instruction pointer (c) Floating-Point Unit Registers Type Number Length (bits) Purpose Numeric 8 80 Hold floating-point numbers Control 1 16 Control bits Status 1 16 Status bits Tag Word 1 16 Specifies contents of numeric registers Instruction Pointer 1 48 Points to instruction interrupted by exception Data Pointer 1 48 Points to operand interrupted by exception © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I V V I A V R N O O D I T S Z A P C 0 0 0 0 0 0 0 0 0 0 I I 0 0 0 1 D C M F T P F F F F F F F F F P F L X ID = Identification flag C DF = Direction flag X VIP = Virtual interrupt pending X IF = Interrupt enable flag X VIF = Virtual interrupt flag X TF = Trap flag X AC = Alignment check S SF = Sign flag X VM = Virtual 8086 mode S ZF = Zero flag X RF = Resume flag S AF = Auxiliary carry flag X NT = Nested task flag S PF = Parity flag X IOPL = I/O privilege level S CF = Carry flag S OF = Overflow flag S Indicates a Status Flag C Indicates a Control Flag X Indicates a System Flag Shaded bits are reserved Figure 14.22 x86 EFLAGS Register © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Floating-Point Tag Floating-Point Registers 79 63 0 00 00 00 00 63 0 00 MM7 00 MM6 00 MM5 00 MM4 MM3 MM2 MM1 MM0 MMX Registers Figure 14.24 Mapping of MMX Registers to Floating-Point Registers © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Interrupt Processing Interrupts and Exceptions ◼ Interrupts ◼ Generated by a signal from hardware and it may occur at random times during the execution of a program ◼ Maskable ◼ Nonmaskable ◼ Exceptions ◼ Generated from software and is provoked by the execution of an instruction ◼ Processor detected ◼ Programmed ◼ Interrupt vector table ◼ Every type of interrupt is assigned a number ◼ Number is used to index into the interrupt vector table © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. Vector Number Description 0 Divide error; division overflow or division by zero 1 Debug exception; includes various faults and traps related to debugging 2 NMI pin interrupt; signal on NMI pin 3 Breakpoint; caused by INT 3 instruction, which is a 1-byte instruction useful for debugging 4 INTO-detected overflow; occurs when the processor executes INTO with the OF flag set 5 BOUND range exceeded; the BOUND instruction compares a register with boundaries stored in memory and generates an interrupt if the contents of the register is out of bounds. Table 14.3 6 Undefined opcode 7 Device not available; attempt to use ESC or WAIT instruction fails due to lack of external device 8 Double fault; two interrupts occur during the same instruction and cannot be handled serially x86 9 Reserved Exception 10 Invalid task state segment; segment describing a requested task is not initialized or not valid and Interrupt 11 Segment not present; required segment not present 12 Stack fault; limit of stack segment exceeded or stack segment not present 13 General protection; protection violation that does not cause another exception (e.g., writing to a Vector Table read-only segment) 14 Page fault 15 Reserved 16 Floating-point error; generated by a floating-point arithmetic instruction 17 Alignment check; access to a word stored at an odd byte address or a doubleword stored at an address not a multiple of 4 18 Machine check; model specific 19-31 Reserved 32-255 User interrupt vectors; provided when INTR signal is activated Unshaded: exceptions Shaded: interrupts © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + The ARM Processor ARM is primarily a RISC system with the following attributes: ◼ Moderate array of uniform registers ◼ A load/store model of data processing in which operations only perform on operands in registers and not directly in memory ◼ A uniform fixed-length instruction of 32 bits for the standard set and 16 bits for the Thumb instruction set ◼ Separate arithmetic logic unit (ALU) and shifter units ◼ A small number of addressing modes with all load/store addresses determined from registers and instruction fields ◼ Auto-increment and auto-decrement addressing modes are used to improve the operation of program loops ◼ Conditional execution of instructions minimizes the need for conditional branch instructions, thereby improving pipeline efficiency, because pipeline flushing is reduced © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  External memory (cache, main memory) Memory address register Memory buffer register Incrementer Sign R15 (PC) extend Rd User Register File (R0 - R15) Rn Rm Acc Instruction register Barrel shifter Instruction decoder Multiply/ ALU accumulate Control unit CPSR Figure 14.25 Simplified ARM Organization © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Processor Modes Most application programs execute in ARM user mode architecture While the processor is in supports seven user mode the program being executed is unable execution to access protected modes system resources or to change mode, other than by causing an exception to occur Remaining six Advantages to defining so many different execution modes privileged modes are referred to as The OS can tailor the use of privileged modes system software to a variety of circumstances These modes are Certain registers are used to run system dedicated for use for each of the privileged modes, allows software swifter changes in context © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. Exception Modes Have full access to system Entered when resources and can specific change modes exceptions occur freely Exception modes: System mode: Supervisor mode Not entered by any exception and uses the Abort mode same registers available Undefined mode in User mode Is used for running certain Fast interrupt mode privileged operating Interrupt mode system tasks May be interrupted by any of the five exception categories © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Modes Privileged modes Exception modes User System Supervisor Abort Undefined Interrupt Fast Interrupt R0 R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8 R8_fiq R9 R9 R9 R9 R9 R9 R9_fiq R10 R10 R10 R10 R10 R10 R10_fiq R11 R11 R11 R11 R11 R11 R11_fiq R12 R12 R12 R12 R12 R12 R12_fiq R13 (SP) R13 (SP) R13_svc R13_abt R13_und R13_irq R13_fiq R14 (LR) R14 (LR) R14_svc R14_abt R14_und R14_irq R14_fiq R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) CPSR CPSR CPSR CPSR CPSR CPSR CPSR SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq Shading indicates that the normal register used by User or System mode has been replaced by an alternative register specific to the exception mode. SP = stack pointer CPSR = current program status register LR = link register SPSR = saved program status register PC = program counter Figure 14.26 ARM Register Organization © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Exception type Mode Normal Description entry address Reset Supervisor 0x00000000 Occurs when the system is initialized. Data abort Abort 0x00000010 Occurs when an invalid memory address has been accessed, such as if there is no physical memory for an address or the correct access permission is lacking. FIQ (fast interrupt) FIQ 0x0000001C Occurs when an external device asserts the FIQ pin on the processor. An interrupt cannot be interrupted except by an FIQ. Table 14.4 FIQ is designed to support a data transfer or channel process, and has sufficient private registers to remove the need for register saving in such applications, therefore minimizing the overhead of context switching. A fast interrupt cannot ARM IRQ (interrupt) IRQ 0x00000018 be interrupted. Occurs when an external device asserts the Interrupt IRQ pin on the processor. An interrupt cannot be interrupted except by an FIQ. Vector Prefetch abort Abort 0x0000000C Occurs when an attempt to fetch an instruction results in a memory fault. The exception is raised when the instruction enters the execute stage of the pipeline. Undefined Undefined 0x00000004 Occurs when an instruction not in the instructions instruction set reaches the execute stage of the pipeline. Software interrupt Supervisor 0x00000008 Generally used to allow user mode programs to call the OS. The user program executes a SWI instruction with an argument that identifies the function the user wishes to perform. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Summary Processor Structure and Function Chapter 14 ◼ Processor organization ◼ Instruction pipelining ◼ Pipelining strategy ◼ Register organization ◼ Pipeline performance ◼ User-visible registers ◼ Pipeline hazards ◼ Control and status registers ◼ Dealing with branches ◼ Instruction cycle ◼ Intel 80486 pipelining ◼ The indirect cycle ◼ The Arm processor ◼ Data flow ◼ Processor organization ◼ The x86 processor family ◼ Processor modes ◼ Register organization ◼ Register organization ◼ Interrupt processing ◼ Interrupt processing © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.