Processor Structure and Function PDF

+ William Stallings Computer Organization and Architecture 10th Edition © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Chapter 14 Processor Structure and Function © 2016 Pearson Education, I...

+ William Stallings Computer Organization and Architecture 10th Edition © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Chapter 14 Processor Structure and Function © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Processor Organization Processor Requirements: Fetch instruction The processor reads an instruction from memory (register, cache, main memory) Interpret instruction The instruction is decoded to determine what action is required Fetch data The execution of an instruction may require reading data from memory or an I/O module Process data The execution of an instruction may require performing some arithmetic or logical operation on data Write data The results of an execution may require writing data to memory or an I/O module In order to do these things the processor needs to store some data temporarily and therefore needs a small internal memory © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Register Organization Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy The registers in the processor perform two roles: User-Visible Registers Control and Status Registers Enable the machine or Used by the control unit to assembly language control the operation of the programmer to minimize processor and by privileged main memory references by operating system programs optimizing use of registers to control the execution of programs © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  User-Visible Registers Categories: Referenced by means General purpose of the machine Can be assigned to a variety of functions by the programmer language that the Data processor executes May be used only to hold data and cannot be employed in the calculation of an operand address Address May be somewhat general purpose or may be devoted to a particular addressing mode Examples: segment pointers, index registers, stack pointer Condition codes Also referred to as flags Bits set by the processor hardware as the result of operations © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Table 14.1 Condition Codes © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Control and Status Registers Four registers are essential to instruction execution: Program counter (PC) Contains the address of an instruction to be fetched Instruction register (IR) Contains the instruction most recently fetched Memory address register (MAR) Contains the address of a location in memory Memory buffer register (MBR) Contains a word of data to be written to memory or the word most recently read © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Program Status Word (PSW) Register or set of registers that contain status information Common fields or flags include: Sign Zero Carry Equal Overflow Interrupt Enable/Disable Supervisor © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Includes the following stages: Instruction Cycle Fetch Execute Interrupt If interrupts are enabled and an Read the next Interpret the opcode interrupt has instruction from and perform the occurred, save the memory into the indicated operation current process state processor and service the interrupt © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Pipelining Strategy To apply this concept to instruction Similar to the use execution we must of an assembly line recognize that an in a manufacturing instruction has a plant number of stages New inputs are accepted at one end before previously accepted inputs appear as outputs at the other end © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Additional Stages Fetch instruction (FI) Fetch operands (FO) Read the next expected instruction into a buffer Fetch each operand from memory Decode instruction (DI) Operands in registers Determine the opcode and need not be fetched the operand specifiers Execute instruction (EI) Calculate operands (CO) Perform the indicated Calculate the effective operation and store the address of each source result, if any, in the operand specified destination operand location This may involve displacement, register Write operand (WO) indirect, indirect, or other Store the result in forms of address memory calculation © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Pipeline Hazards Occur when the pipeline, or some portion of the pipeline, must stall There are three because conditions types of hazards: do not permit Resource continued Data execution Control Also referred to as a pipeline bubble © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Types of Data Hazard Read after write (RAW), or true dependency An instruction modifies a register or memory location Succeeding instruction reads data in memory or register location Hazard occurs if the read takes place before write operation is complete Write after read (WAR), or antidependency An instruction reads a register or memory location Succeeding instruction writes to the location Hazard occurs if the write operation completes before the read operation takes place Write after write (WAW), or output dependency Two instructions both write to the same location Hazard occurs if the write operations take place in the reverse order of the intended sequence © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Control Hazard Also known as a branch hazard Occurs when the pipeline makes the wrong decision on a branch prediction Brings instructions into the pipeline that must subsequently be discarded Dealing with Branches: Multiple streams Prefetch branch target Loop buffer Branch prediction Delayed branch © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Multiple Streams A simple pipeline suffers a penalty for a branch instruction because it must choose one of two instructions to fetch next and may make the wrong choice A brute-force approach is to replicate the initial portions of the pipeline and allow the pipeline to fetch both instructions, making use of two streams Drawbacks: With multiple pipelines there are contention delays for access to the registers and to memory Additional branch instructions may enter the pipeline before the original branch decision is resolved © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Prefetch Branch Target When a conditional branch is recognized, the target of the branch is prefetched, in addition to the instruction following the branch Target is then saved until the branch instruction is executed If the branch is taken, the target has already been prefetched + IBM 360/91 uses this approach © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Loop Buffer Small, very-high speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions, in sequence Benefits: Instructions fetched in sequence will be available without the usual memory access time If a branch occurs to a target just a few locations ahead of the address of the branch instruction, the target will already be in the buffer This strategy is particularly well suited to dealing with loops Similar in principle to a cache dedicated to instructions Differences: The loop buffer only retains instructions in sequence Is much smaller in size and hence lower in cost © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Branch Prediction Various techniques can be used to predict whether a branch will be taken: 1. Predict never taken These approaches are static 2. Predict always taken They do not depend on the execution history up to the time 3. Predict by opcode of the conditional branch instruction 4. Taken/not taken switch These approaches are dynamic 5. Branch history table They depend on the execution history © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Intel 80486 Pipelining Objective is to fill the prefetch buffers with new data asFetch Operates independently of the other stages to keep the soon as the old data have been consumed by the prefetch buffers full instruction decoder Decode stage 1 D1 decoder can then direct the D2 All opcode and addressing-mode 3 bytes of instruction are passed to stage to capture the rest of the information is decoded in the D1 stage the D1 stage from the prefetch buffers instruction Decode stage 2 Also controls the computation of the more complex Expands each opcode into control signals for the ALU addressing modes Execute Stage includes ALU operations, cache access, and register update Write back Updates registers and status flags modified during the preceding execute stage © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Table 14.2 x86 Processor Registers © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Interrupt Processing Interrupts and Exceptions Interrupts Generated by a signal from hardware and it may occur at random times during the execution of a program Maskable Nonmaskable Exceptions Generated from software and is provoked by the execution of an instruction Processor detected Programmed Interrupt vector table Every type of interrupt is assigned a number Number is used to index into the interrupt vector table © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Table 14.3 x86 Exception and Interrupt Vector Table Unshaded: exceptions Shaded: interrupts © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + The ARM Processor ARM is primarily a RISC system with the following attributes: Moderate array of uniform registers A load/store model of data processing in which operations only perform on operands in registers and not directly in memory A uniform fixed-length instruction of 32 bits for the standard set and 16 bits for the Thumb instruction set Separate arithmetic logic unit (ALU) and shifter units A small number of addressing modes with all load/store addresses determined from registers and instruction fields Auto-increment and auto-decrement addressing modes are used to improve the operation of program loops Conditional execution of instructions minimizes the need for conditional branch instructions, thereby improving pipeline efficiency, because pipeline flushing is reduced © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Processor Modes Most application ARM programs execute architecture in user mode supports While the processor is in user mode the seven program being executed is unable to execution access protected modes system resources or to change mode, other than by causing an exception to occur Remaining six Advantages to defining so many execution different privileged modes are modes referred to as The OS can tailor the use of system software to a privileged variety of circumstances modes Certain registers are dedicated for use for each These modes are of the privileged modes, used to run system allows swifter changes in context software © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. Exception Modes Have full access Entered when to system specific resources and exceptions can change occur modes freely Exception System mode: modes: Not entered by any exception and uses the Supervisor mode same registers available Abort mode in User mode Is used for running Undefined mode certain privileged Fast interrupt operating system tasks mode May be interrupted by Interrupt mode any of the five exception categories © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Table 14.4 ARM Interrupt Vector © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Summary Processor Structure and Function Chapter 14 Processor organization Instruction pipelining Pipelining strategy Register organization Pipeline performance User-visible registers Pipeline hazards Control and status registers Dealing with branches Intel 80486 pipelining Instruction cycle The indirect cycle The Arm processor Data flow Processor organization Processor modes The x86 processor family Register organization Register organization Interrupt processing Interrupt processing © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.