Computer Organization PDF

CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 1 LESSON OUTCOMES Upon completion of this chapter, students should be able to: identify, explain, and understand peripheral roles and connections. assess speed and coordination issues...

CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 1 LESSON OUTCOMES Upon completion of this chapter, students should be able to: identify, explain, and understand peripheral roles and connections. assess speed and coordination issues. understand the programmed I/O techniques. Understand the I/O modules for data transfer. grasp interrupts, stack management, and endian formats. understand the DMA and evaluate its benefits. compare bus and channel architectures. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 2 1  INTRODUCTION I/O (Input/Output) architecture refers to the design and structure of the system responsible for managing and facilitating communication between a computer system's central processing unit (CPU) and its peripheral devices (such as disks, keyboards, mice, printers, network interfaces, and other hardware). It plays a critical role in ensuring efficient data transfer, effective use of system resources, and overall system performance. This architecture encompasses the hardware, software, and protocols involved in the data transfer process. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 3 PERIPHERALS CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 4 2  PERIPHERALS Peripherals are external devices connected to a computer that provide input, output, or storage functions, enhancing the computer's capabilities. Devices that are separate from the basic computer - not the CPU, memory, and power supply. They can be classified into three main categories: Input Devices Output Devices Storage Devices CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 5 CONCEPTUAL OVERVIEW OF A COMPUTER SYSTEM CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 6 3  PERIPHERALS Input Devices These peripherals allow users to input data and commands into the computer. Examples include: Keyboard: Used for typing text and commands. Mouse: Used for pointing, clicking, and dragging objects on the screen. Scanner: Converts physical documents into digital format. Microphone: Captures audio input. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 7 PERIPHERALS Output Devices These devices display or output data from the computer to the user. Examples include: Monitor: Displays visual output from the computer. Printer: Produces physical copies of digital documents. Speakers: Output audio from the computer. Projector: Displays computer output on a larger screen. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 8 4  PERIPHERALS Storage Devices These peripherals store data for long-term retention. Examples include: External Hard Drive: Provides additional storage space. USB Flash Drive: Portable storage device. CD/DVD/Blu-ray Drives: Read and write optical discs. Network Attached Storage (NAS): Provides storage over a network. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 9 PERIPHERAL INTERFACING Peripherals connect to the computer through various interfaces and ports, such as: USB (Universal Serial Bus): Common interface for many peripherals. HDMI (High-Definition Multimedia Interface): For video and audio output. Bluetooth: Wireless connection for devices like keyboards, mice, and speakers. Ethernet: Wired network connection for devices like printers and NAS. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 10 5  PERIPHERALS Importance of Peripherals Enhance Functionality: Extend the capabilities of a computer beyond its core functions. User Interaction: Facilitate user interaction with the computer, making it easier to input and receive data. Specialized Tasks: Enable the computer to perform specialized tasks, such as printing, scanning, and audio recording. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 11 I/O CONSIDERATION CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 12 6  INTRODUCTION When designing and managing input/output (I/O) systems, speed and coordination are critical factors to consider to ensure efficient and reliable data transfer between the computer and its peripherals. TWO I/O consideration: Speed Coordination CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 13 SPEED CONSIDERATION CPU operates at speeds much faster than the fastest I/O device Modern CPUs operate at incredibly high speeds, often measured in gigahertz (GHz), which far exceed the speeds of typical I/O devices such as hard drives, USB flash drives, or network interfaces. This speed disparity can lead to a bottleneck where the CPU may have to wait for data from slower I/O devices, causing performance degradation and inefficiency in processing tasks. To mitigate this issue, techniques such as buffering, caching, and parallel processing can be employed. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 14 7  SPEED CONSIDERATION Devices operate at different speeds In an I/O system, various peripheral devices operate at different speeds depending on their capabilities and the type of data they handle. When multiple devices with varying speeds are connected to the same system, managing data transfers efficiently becomes challenging. Slow devices may introduce delays in data processing, affecting overall system performance. Implementing adaptive algorithms or prioritization schemes can help manage data transfers based on device speeds. For instance, faster devices may be given priority in data processing queues to minimize wait times for critical tasks. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 15 SPEED CONSIDERATION Bursts of data Bursty data is when a lot of data is transferred very quickly in a short amount of time Bursty data can overwhelm I/O systems, causing congestion, increased latency, and potential data loss or corruption if not handle efficiently. Employing buffering and flow control mechanisms can help manage bursty data. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 16 8  SPEED CONSIDERATION Block data transfer required for some devices Some I/O devices, such as hard drives or SSDs, perform data transfers in blocks or sectors rather than individual bytes. Block data transfers can introduce overhead, especially when dealing with small amounts of data or when the block size is not optimal for the application. Optimizing block sizes based on the specific I/O device and application requirements can improve efficiency. Additionally, using DMA (Direct Memory Access) for block data transfers can reduce CPU involvement and enhance data transfer speeds. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 17 COORDINATION CONSIDERATION Several devices perform I/O simultaneously When multiple devices perform input/output (I/O) operations simultaneously, coordination becomes crucial to ensure efficient and error-free data transfer. Unexpected input Unexpected input refers to data or signals received by the I/O system that were not anticipated or handled properly. Various input formats Different devices may produce or expect data in various formats (e.g., text, binary, serialized objects), requiring coordination to ensure compatibility and proper data processing. Status information needed for each device Devices often require status information (e.g., device readiness, data availability) from the I/O system to coordinate their operations effectively. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 18 9  INPUT/OUTPUT MODULE CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 19 I/O MODULE An I/O module serves as an interface between the CPU and the peripheral devices (such as keyboards, mice, printers, and storage devices). It manages the communication and data transfer between the CPU and these external devices, ensuring that data is correctly formatted, buffered, and synchronized for effective input and output operations. An I/O module is the entity within the computer responsible for: the control of one or more external devices. The exchange of data between those devices and main memory and/or CPU. The disk controller is an example of an I/O module. A disk drive – accepting commands from the CPU on one side and controlling the device on the other. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 20 10  I/O MODULE An I/O module or control unit module used to control a peripheral device is known as a device controller. Example: disk controller (disk drive module), network interface controller (network module) A device controller accepts IO requests and interacts directly with the device to satisfy those requests. The I/O modules receive messages from the CPU, control the device, initiate and control DMA when required, and produce interrupts. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 21 I/O MODULE The I/O modules perform 2 different function: 1. At the CPU interface, the module performs CPU interfacing tasks such as accepting I/O commands from the CPU, transferring data between the module and the CPU or memory and sending interrupts and status information to the CPU. 2. At the device interface, the I/O module supplies control of the device such as moving the head to the correct track in a disk drive and rewinding tape. CPU IO Module CPU Device I/O device interface interface CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 22 11  I/O MODULES FUNCTIONS Recognizes messages from device(s) addressed to it and accepts commands from the CPU Provides a buffer where the data from memory can be held until it can be transferred to the device Provides the necessary registers and controls to perform a direct memory transfer Physically controls the device Controls the disk drive, moving the head to the physically location on the disk where data is to be written Copies data from its buffer to the device/from the CPU to its buffer Communicates with CPU It notify the CPU when the transfer is complete. It interrupt the CPU to notify it of errors or problem that arise during the transfer. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 23 BUFFERING A method where a buffer holds the data and release a part of it at specific times. holding & releasing parts of data at specific times A region of memory used to temporarily hold data while it is being moved from one place to another. Holding Data: Data from an I/O device is temporarily stored in a buffer until the CPU is ready to process it, managing differences in data transfer rates. Releasing Data: The CPU places data into a buffer for the I/O device, which then holds it until the device is ready to receive it, allowing the CPU to perform other tasks. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 24 12  BUFFERING Examples: Keyboard Input When a user types on a keyboard, each keystroke generates an interrupt. The data for each keystroke is held in a buffer until the CPU is ready to process the input. The CPU can then read the buffered data in larger chunks rather than handling each keystroke individually, reducing the number of interrupts and improving efficiency. Disk I/O When reading from or writing to a disk, data is transferred in blocks. The disk controller uses a buffer to hold the data being read from or written to the disk. For read operations, the buffer accumulates data from the disk and then releases it to the CPU in larger chunks. For write operations, the CPU writes data to the buffer, which then releases it to the disk. This buffering allows for efficient disk operations, reducing the time the CPU spends waiting for the disk and allowing it to perform other tasks. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 25 HANDSHAKING Handshaking is a process that takes place when a computer is about to communicate with a foreign device to establish rules for communication. A brief back-and-forth series of requests and acknowledgements to request a connection. If the negotiation is successful, a connection is opened. This connection is logically a full-duplex connection. A web browser application use this technique to establish connection on the Internet. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 26 13  HANDSHAKING PROCESS When a computer is about to communicate with a foreign device (such as a printer, keyboard, or Initialization network interface), it first initiates the handshaking process. This involves sending a signal to the device to indicate that it wants to start communication. Establishing The computer and the foreign device exchange control signals to establish the parameters for communication. These parameters can include data transfer rates, error-checking methods, and data Communication Rules formats. Handshaking ensures that both the computer and the device are synchronized, meaning that data is Synchronization transferred only when both parties are ready. This prevents data loss and errors. Once the handshaking process is complete and both devices are synchronized, data transfer can Data Transfer begin. The established rules and synchronization ensure that data is transferred accurately and efficiently. After the data transfer is complete, the devices may send final signals to indicate the end of Completion communication. This ensures that both the computer and the device are aware that the communication session has concluded CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 27 HANDSHAKING PROCESS CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 28 14  I/O TECHNIQUES There are THREE types of I/O communication techniques: Programmed I/O: In this case, the transfer of data from an I/O device to the memory will require the CPU to initiate a program. The CPU remains in a loop until the I/O device is prepared to make the data transfer. Interrupt Driven I/O: In this case, the CPU offers a read command to the I/O device and once the I/O device is prepared to transfer data, it sends an interrupt signal to the processor. Upon this event, the CPU then checks the status of the device and will write that information into the memory if it is ready. Direct Memory Access (DMA): In this communication technique, the I/O device can both send and receive data directly from the memory, bypassing the CPU altogether and enhancing the speed of memory operations. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 29 PROGRAMMED I/O CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 30 15  PROGRAMMED I/O Programmed I/O (PIO) is a method used by a CPU to directly control the data transfer between itself and peripheral devices, such as keyboards, printers, and storage devices. In this approach, the CPU is heavily involved in the data transfer process, issuing commands and waiting for operations to complete before moving on to the next task. The CPU is actively involved in the data transfer, issuing commands and waiting for the operations to complete. Programmed I/O is more effective for small amounts of data, particularly when speeds are extremely slow. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 31 PROGRAMMED I/O Poll and response is a process where the CPU repeatedly checks (polls) the status of an I/O device to see if it is ready for data transfer (input or output). "poll and response" in programmed I/O means that the CPU actively waits and checks (polls) for the device’s readiness before proceeding with the data transfer (response). This process continues for each piece of data that needs to be transferred, making it a straightforward but potentially inefficient method due to the constant involvement of the CPU. This method ensures the CPU directly controls and monitors the I/O operations, but it can be inefficient because the CPU spends a lot of time checking the device status instead of performing other tasks. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 32 16  PROGRAMMED I/O Polling Technique/approach to taking care of peripheral devices by checking each device in rotation at frequent intervals to see if it need service. Polling is when the CPU repeatedly checks the status of a peripheral device to see if it is ready for data transfer. This involves the CPU continuously asking the device, "Are you ready yet?“ Response Response occurs when the peripheral device indicates it is ready. At this point, the CPU can proceed with the data transfer. The CPU then reads data from or writes data to the device. Disadvantages of polling The computer time spent in polling is largely wasted. Not efficient when the processor needs to perform other tasks or multiple tasks. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 33 PROGRAMMED I/O How Programmed I/O Works Initiation: The CPU issues a command to the peripheral device by writing to its control register. This could be a command to read data from or write data to the device. Polling: The CPU continuously checks the status of the peripheral device to determine if it is ready for data transfer. This is often referred to as "polling.“ Data Transfer: Once the device indicates it is ready (through a status register or similar mechanism), the CPU reads data from or writes data to the device. This process is repeated for each byte or word of data to be transferred. Completion: The CPU completes the data transfer operation and moves on to the next task. If more data needs to be transferred, the CPU repeats the process. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 34 17  INTERRUPT-DRIVEN I/O CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 35 INTERRUPT-DRIVEN I/O Interrupt-driven I/O is a method used in computer systems where the CPU initiates an I/O operation with a peripheral device and then continues executing other tasks. When the I/O operation is complete or requires attention (e.g., data is ready), the device sends an interrupt request (IRQ) to the CPU. The CPU interrupts its current task, transfers control to an interrupt handler routine, processes the I/O operation, and then resumes the interrupted task. This asynchronous approach allows for efficient handling of multiple I/O operations and improved system responsiveness compared to programmed I/O. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 36 18  INTERRUPT-DRIVEN I/O Module calls CPU when needed in interrupt-driven I/O signifies the efficient communication and interaction between peripheral modules and the CPU, where modules only initiate communication or request CPU attention when necessary, reducing unnecessary overhead and improving system efficiency. In interrupt-driven I/O, the concept of "module calls CPU when needed" refers to the interaction between peripheral devices (modules) and the central processing unit (CPU) in a computer system. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 37 INTERRUPT-DRIVEN I/O Module: A module refers to a peripheral device such as a disk drive, network interface, or keyboard connected to the computer system. Each module has its own functionality and communicates with the CPU as needed for data transfer or to signal events. CPU Interaction: In interrupt-driven I/O, modules do not constantly communicate with the CPU. Instead, they initiate communication or notify the CPU only when necessary, such as when data is ready for transfer, an operation is completed, or an error occurs. Interrupt Requests (IRQs): When a module needs the CPU's attention, it sends an interrupt request (IRQ) signal. This IRQ interrupts the CPU's current execution and triggers the CPU to handle the module's request or event. Interrupt Handler: The CPU responds to the IRQ by transferring control to a specific part of the operating system called an interrupt handler or interrupt service routine (ISR). The interrupt handler is responsible for processing the module's request, whether it involves data transfer, error handling, or other actions. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 38 19  INTERRUPT-DRIVEN I/O Summary: Overcome CPU waiting. No repeated CPU checking of device. I/O module interrupts when ready. Still requires CPU to be go between for moving data between I/O module and main memory. Interrupt-driven I/O approach allows the CPU to focus on executing other tasks or processes until a module requires attention, therefore it prevents the CPU from continuously polling or checking the status of all modules, which would waste resources and decrease system efficiency (efficient resource utilization). Interrupt-driven I/O enables asynchronous operation, meaning that the CPU can handle multiple tasks concurrently without being blocked by I/O operations, so it improves system responsiveness and overall performance. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 39 INTERRUPT What is an interrupt? A call for the microprocessor to interact or service the interrupting unit Signal that causes the CPU to alter its normal flow on instruction execution frees CPU from waiting for events provides control for external input Examples: unexpected input, abnormal situation, illegal instructions, multitasking, multiprocessing. There are two type of interrupts Hardware interrupt – this interrupt is being sent by the peripheral devices to indicate certain conditions such as keyboard entry, printing problem, and power failure Software interrupt – modern CPU has a set of instructions to simulates an interrupt for examples are HLT and INT CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 40 20  INTERRUPT Interrupt causes the temporary suspension of the program in progress. All the information about the program being suspended, including the last location of the last instruction executed, and the values of data in various registers, is saved in a known part of memory (either in a special area associated with the program, known as the process control block (PCB), or in a part of memory known as the stack area) The computer then branches to a special interrupt handler program elsewhere in memory the interrupt handler program is also known as an interrupt routine or an interrupt service routine The interrupt handler program determines the appropriate course of action. This process is known as servicing the interrupt. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 41 INTERRUPT: SERVICING THE INTERRUPT There are four steps taken by microprocessor to handle an interrupt: 1. The microprocessor finished the current instruction until the end of an instruction cycle 2. Normal operation is suspended 3. The microprocessor jumps to the location in memory where the interrupt service routine has been stored and executes the routines 4. When the interrupt routines complete, it would return control to the interrupted program CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 42 21  INTERRUPT: SERVICING THE INTERRUPT Interrupt Normal Execution 1) Finish Current Instruction Suspend Operation Contents of registers 2) Store Registers stored in stack 3) Jump to Interrupt Routine and Execute 4) Return to Normal Operation Contents of registers returned from stack Restore MP Status Normal Execution Continues CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 43 INTERRUPT: SERVICING THE INTERRUPT CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 44 22  THE USES OF INTERRUPTS The way which an interrupt is used depend on the nature of the devices There are several ways in which interrupt are used: As an external event notifier As a completion signal As a means of allocating CPU time As an abnormal event indicator CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 45 THE USES OF INTERRUPTS The Interrupt As An External Event Notifier To indicate some external devices, require action Frees CPU from polling, a means for the user to control the computer from an input device An example is keyboard input CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 46 23  THE USES OF INTERRUPTS The Interrupt As A Completion Signal To control the flow of data to an output device Interrupt serves to notify the computer completion of a particular course of action Means of controlling the flow of data to an external device (i.e. printer ready or buffer full) telling the computer to stop sending data temporarily when the printer’s buffer fills up. An example is printing process and DMA process. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 47 THE USES OF INTERRUPTS The Interrupt As A Means Of Allocating CPU Time Time sharing Used as a method of allocating CPU time to different programs that are sharing the CPU The computer system provides an internal clock that sends an interrupt periodically to the CPU Once the CPU receive the interrupt, it will suspend the current program and go to the next program to be executed CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 48 24  THE USES OF INTERRUPTS The Interrupt As An Abnormal Event Indicator Used to handle abnormal events that effect the operation of the computer The events are directly at the problems within the computer system itself An example is execution of an illegal instructions such as division by zero, nonexistent code, and hardware error such as power failure Internal interrupts are sometimes called traps or exceptions CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 49 THE USES OF INTERRUPTS SOFTWARE INTERRUPTS Modern CPU instruction sets include an instruction that simulates an interrupt. In the Intel x86 architecture, for example, this instruction has the mnemonic INT, for INTERRUPT. The interrupt instruction works in the same way as a hardware interrupt, saving appropriate registers and transferring control to an interrupt handling procedure. The address space of the INT instruction can be used to provide a parameter that specifies which interrupt is to be executed. The software interrupt is very similar to a subroutine jump to a known, fixed location. Software interrupts make the interrupt routines available for use by other programs. Software interrupts are used by each program to request I/O from the operating system software. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 50 25  MULTIPLE INTERRUPTS Multiple interrupts will occur from time to time Are there other interrupts already awaiting service, and if so, how does the computer determine the order in which the interrupts get serviced? How does the computer identify the interrupting device? Two different processing methods used to determine which devices initiated the interrupt: 1. vectored interrupt 2. polling CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 51 MULTIPLE INTERRUPTS Vectored Interrupt The address of the interrupting devices is included as part of the interrupt The vectored interrupt is faster than polling but requires additional hardware to implement CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 52 26  MULTIPLE INTERRUPTS Polled Interrupt Checking for input in rotation Provides a general interrupt that is shared by all devices The computer identifies the interrupting device by polling each device when the interrupt occurs. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 53 MULTIPLE INTERRUPTS & PRIORITIZATION Multiple interrupts can be handled by assigning priorities to each interrupt A higher-priority interrupts can interrupt other interrupts of lower priority, but a lower-priority interrupts will have to wait until a higher-priority interrupt is completed. Priorities are established in a logical way: Highest priorities are reserved for time-sensitive situations, such as power failure or external events that are being time measured. Task completion interrupts usually take lower priorities, since the delay will not affect the integrity of the data under normal conditions. For example: Keyboard events are also usually considered high-priority events, since data loss can occur if the keyboard input is not read quickly. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 54 27  MULTIPLE INTERRUPTS & PRIORITIZATION The figure shows a simple example of this situation. In this figure, interrupt routine C is the highest priority, followed by B and A CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 55 CATEGORIES OF INTERRUPTS Maskable Interrupt A type of hardware interrupt that can be turned off or "masked" by the CPU, meaning the processor can temporarily ignore this interrupt under certain conditions. the interrupt will not be accepted (can be selectively disabled) This allows the CPU to prioritize other tasks or higher-priority interrupts without being disrupted by the maskable interrupt. Non-maskable Interrupt A type of hardware interrupt that cannot be ignored or "masked" by the CPU. the interrupt will always be acknowledged and accepted, such as a power failure This means the processor must respond to an NMI immediately, regardless of the current state of the system or any other interrupts that might be occurring. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 56 28  MULTIPLE INTERRUPTS & PRIORITIZATION Final Exam Question Apr 2003 Describe the steps that occur when a system receives multiple interrupts. 1. System will handle top priority first. 2. A higher priority interrupt will be allowed to interrupt an interrupt of lower priority. 3. Lower priority interrupt will have to wait until a higher priority interrupt is completed. Give TWO advantages of the polling concepts. 1. Not efficient when the CPU needs to perform other tasks. 2. CPU time spent in polling is largely wasted. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 57 DIRECT MEMORY ACCESS (DMA) CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 58 29  DIRECT MEMORY ACCESS (DMA) Direct Memory Access (DMA) is a feature in computer systems that allows certain hardware components, such as disk drive controllers, graphics cards, or network cards, to directly read from and write to the main memory (RAM) without involving the CPU. Method of transferring data from the computer's RAM to another part of the computer without processing it using the CPU While most data that is input or output from your computer is processed by the CPU, some data does not require processing, or can be processed by another device. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 59 DIRECT MEMORY ACCESS (DMA) This can significantly improve performance by freeing the CPU from being the intermediary for these data transfers, allowing it to perform other tasks. DMA can save processing time and is a more efficient way to move data from the computer's memory to other devices. Useful any time the CPU cannot keep up with the rate of data transfer, or where the CPU needs to perform useful work while waiting for a relatively slow I/O data transfer. With DMA, the CPU initiates the transfer, does other operations while the transfer is in progress, and receives an interrupt from the DMA controller when the operation is done. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 60 30  DIRECT MEMORY ACCESS (DMA) Required conditions for DMA: The I/O interface and memory must be connected There must be a method to connect the I/O interface and memory. In some systems, both are already connected to the same bus, which simplifies this requirement. In other cases, the system design must include provisions for interconnecting the two. The I/O module must be capable of reading and writing to memory The I/O module associated with the specific device must be capable of reading from and writing to memory. It achieves this by simulating the CPU’s interface with memory, which includes the ability to load a memory address register and to read and write to a memory data register. Conflicts between the CPU and the I/O module must be avoided Both the CPU and the DMA controller might need access to the memory simultaneously. If not managed properly, this could lead to conflicts, causing data corruption or system crashes. Typically, this is handled through bus arbitration, where a priority system determines whether the CPU or the DMA controller gets access to the bus at any given time. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 61 DIRECT MEMORY ACCESS (DMA) Example: A sound card may need to access data stored in the computer's RAM, but since it can process the data itself, it may use DMA to bypass the CPU. Video cards that support DMA can also access the system memory and process graphics without needing the CPU. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 62 31  DMA INSTRUCTIONS Application program requests I/O service from operating system privileged programmed I/O instructions To initiate DMA, programmed I/O is used to send the following information: 1. The location of the data on the I/O device (for example, the location of the block on 2. the disk). 3. The starting location of the block of data in memory. 4. The size of the block to be transferred. 5. The direction of transfer, read (I/O → memory) or write (memory → I/O). Interrupt to CPU upon completion of DMA CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 63 DMA INSTRUCTIONS CPU send signal to DMA to start data transfer. CPU sets up a device such as a disk drive for DMA transfer, and disables DMA interrupts CPU perform other instructions and DMA control the data transfer. Data is transferred into DMA memory, while the CPU is freed to handle other tasks. DMA send a signal to CPU when the transfer was finished. Once the data transfer is completed, the CPU is interrupted to allow it to handle cleanup after the DMA transfer. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 64 32  DIRECT MEMORY ACCESS (DMA) Summary: With DMA, I/O module and main memory exchange data directly, without CPU involvement DMA allows certain hardware to access main system memory independently of the CPU Direct transfer to and from memory DMA is used for large blocks/volumes of data transfer CPU not actively involved in transfer itself. In DMA, the data transfer is managed by the DMA controller, which allows the CPU to perform other tasks while the transfer is ongoing When the transfer is complete, the DMA module sends an interrupt signal to the CPU. The CPU is involved only at the beginning and end of the transfer. Many hardware systems use DMA including disk drive controllers, graphic cards, network cards and sound cards. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 65 DIRECT MEMORY ACCESS (DMA) Final Exam Question Oct 2008 State TWO advantages of DMA over programmed I/O. 1. Reduced CPU Overhead - In DMA, the data transfer is managed by the DMA controller, which allows the CPU to perform other tasks while the data transfer is being processed. 2. Faster Data Transfer - DMA can transfer data directly between memory and peripherals at high speeds, without involving the CPU for each byte or word transferred. Well suited for high-speed disk transfer like disk drives and network cards. Name any TWO input/output devices that would require DMA technique. 1. Hard Disk Drives (HDDs) and Solid-State Drives (SSDs) 2. Network Interface Cards (NICs) 3. Graphics Cards (GPUs) 4. Sound Cards CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 66 33  DIFFERENCES BETWEEN PROGRAMMED IO, INTERRUPT-DRIVEN IO AND DMA Programmed IO Interrupt-Driven IO DMA The CPU is responsible for directly controlling all data The CPU initiates a data transfer and then continues A separate hardware component (the DMA controller) manages transfers between memory and I/O devices. with other tasks. the data transfer between memory and I/O devices. The CPU continuously checks the status of the I/O The I/O device interrupts the CPU when it is ready The CPU initiates the transfer by configuring the DMA controller device and transfers data byte by byte or word by to transfer data or needs attention, allowing the CPU and then can continue with other tasks. The DMA controller word. to process other tasks in the meantime. handles the actual data transfer. Advantages: Advantages: Advantages: Simple to implement and understand. More efficient than programmed I/O as the CPU is Minimal CPU involvement, as the DMA controller manages the Suitable for low-speed devices and simple not constantly polling the device. entire data transfer process. applications. Better system performance, as the CPU can perform High efficiency and performance, especially for large or high- other tasks while waiting for I/O operations to speed data transfers, as the CPU is free to perform other tasks. complete. Ideal for high-throughput devices like disk drives and network cards. Disadvantages: Disadvantages: Disadvantages: High CPU involvement, leading to inefficiency as the Still involves the CPU in the data transfer process, More complex hardware design and implementation. CPU is busy checking device status and transferring as the CPU must handle the interrupts and manage Requires additional hardware (the DMA controller), which can data. the data transfer. add to system cost. Poor system performance, especially when handling Can be complex to implement, as it requires an multiple I/O devices or high-speed devices, as the interrupt handling mechanism. CPU is constantly occupied with I/O tasks. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 67 DIFFERENCES BETWEEN PROGRAMMED IO, INTERRUPT-DRIVEN IO AND DMA Feature Programmed I/O Interrupt-Driven I/O Direct Memory Access (DMA) CPU Involvement High Medium Low Efficiency Low Medium High Complexity Simple Medium Complex Performance Poor Better Best Use Case Low-speed devices, simple Moderate-speed devices, High-speed devices, large applications multitasking environments data transfers CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 68 34  CPU–MEMORY–I/O ARCHITECTURE CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 69 CPU – MEMORY – I/O ARCHITECTURE FIVE basic components involved in the interface between the CPU and the I/O peripheral: The CPU The I/O peripheral device Memory One or more I/O modules Act as an interface between the CPU or memory and one or more I/O devices. The primary role of the I/O module is to receive commands from the CPU and to provide the control of the I/O device(s) so as to execute those commands. Buses - connecting the various components together CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 70 35  CPU – MEMORY – I/O ARCHITECTURE Basic CPU-Memory-I/O Pathway 2 4 Memory 3 1 CPU I/O Module I/O Device Buses 5 CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 71 CPU – MEMORY – I/O ARCHITECTURE TWO basic I/O system architectures in common use: 1. Bus architecture A system design where a single communication pathway, known as a bus, is shared among multiple hardware components for the purpose of data transfer. This architecture facilitates communication between the CPU, memory, and peripheral devices within a computer system. Used in almost all PCs, workstations, and low-to mid-range servers 2. Channel architecture A computing system design that utilizes dedicated communication pathways, known as channels, to facilitate high-speed data transfer between the CPU, memory, and peripheral devices. The channel architecture provides each device with its own dedicated pathway or channel. Found primarily in mainframe computers and high-performance servers. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 72 36  I/O BUS ARCHITECTURE A bus forms the backbone for connection of the various components, memory and I/O, to the CPU. A single system bus connects the CPU to memory and to all the various modules that control I/O devices. The system bus in a bus architecture consists of a numbers of different interconnected buses. The system bus organization of a PC, for example, often consists of a CPU bus, a PCI bus, and sometimes an ISA bus. The various buses in a PC are interconnected by bus interfaces, sometimes known as expansion bus interfaces or bus bridges. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 73 I/O BUS ARCHITECTURE A general bus interface configuration CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 74 37  I/O BUS ARCHITECTURE Bus interfaces expand the flexibility of the system bus architecture by converting the bus signals from one bus to another so that different types of buses can be used together The ability to interconnect buses: makes possible the design and use of industry standard buses on equipment of different vendors (leads to the concept of open architectures) provides flexibility for the future; as bus designs evolve, new bus interfaces can be implemented to add the capabilities of new & improved buses to the system Each bus provides the necessary data and address lines, lines for interrupt, and various lines to control timing, reads and writes, and so on. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 75 I/O BUS ARCHITECTURE The major differences, other than specifications, actual pin assignments, and physical differences, lie in the way the control signals are implemented. ISA Bus PCI Bus Data width = 16-bit Data width = 32-bit or 64-bit Has separate data and address lines Address and data share same lines using the multiplexing technique - Designed to transfer several pieces of data in a rapid sequence called a burst once a starting address is established CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 76 38  BUS CHARACTERISTICS Buses are characterized primarily by their: Configuration Number of separate conductors Width bits carried simultaneously Addressing capacity Speed Lines on the bus are for a single type of signal or shared Distance between two endpoints Usage Type of control required Features and capabilities A bus will operate according to an associated protocol. Bus may be designed for use within the CPU, as interconnections between major system components, and between the system and external devices. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 77 CATEGORY OF BUSES Parallel A bus in which there is an individual line for each bit of data, address and control being used. Data can be transferred simultaneously. High throughput because all bits of a word are transmitted simultaneously. Expensive and require large number of lines. Used for internal and short external distances such as CPU buses and on computer motherboards. Serial A bus in which data is transferred sequentially, one bit at a time using a single data line pair Low throughput because data is transferred sequentially, one bit a time. Used for longer distance. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 78 39  BUS TOPOLOGY Point-to-point bus a bus that carry signals from a specific source to specific destination single source to single destination example: the cable that connects the parallel or serial port in a PC from the computer to a printer Multipoint bus (multidrop bus/broadcast bus) a bus used to connect several points together the signals produced by a source on the bus are “broadcast” to every other point on the bus requires addressing signals to identify the desired destination example: the Ethernet network CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 79 POINT-TO-POINT VS. MULTIPOINT Plug-in Broadcast bus device Example: Ethernet Shared among multiple devices CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 80 40  I/O CHANNEL ARCHITECTURE The channel architecture is based on a separate I/O processor known as a channel subsystem I/O processor acts as separate computer just for I/O operations, thus freeing the CPU for other tasks The channel subsystem executes its own set of instructions, known as channel control words, independent of the CPU Channel control words are stored as “programs” in memory, just like other computer instructions CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 81 I/O CHANNEL ARCHITECTURE The channel subsystem is made up of subchannels, each of which is connected through a control unit module to an individual device by one or more channel paths. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 82 41  I/O CHANNEL ARCHITECTURE The design allows multiple channel paths between the channel subsystem and the CU, so that if one is busy another can be selected Up to 8 different channel paths can exist for a particular I/O device Channel paths can also be used to interconnect computers into cluster Physically, the channel subsystem is connected to the CPU by a bus, and the various control units and I/O devices are also connected by buses BUT conceptually, the channel architecture is very different CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 83 I/O BUS ARCHITECTURE vs. I/O CHANNEL ARCHITECTURE I/O BUS ARCHITECTURE I/O CHANNEL ARCHITECTURE IO Bus Architecture connects the CPU, memory, and various peripheral IO Channel Architecture uses dedicated channels to manage I/O devices via a shared communication pathway called a bus. operations between the CPU and peripheral devices. Separates the I/O subsystem from the CPU by using dedicated channels to handle I/O operations All devices share the same bus for communication. Each device has its dedicated channel for specific types of I/O Data transfers are managed via bus protocols, with devices taking turns operations. to use the bus. More efficient and organized as channels can operate independently and concurrently. Straightforward design and implementation. Higher performance due to reduced contention and parallel operation of Cheaper to implement because it requires fewer physical connections. channels. Easier to scale as additional channels can be added without significantly impacting existing ones. Can become a bottleneck if many devices try to communicate More complex to design and implement. simultaneously, leading to contention and delays. More expensive due to the need for additional hardware and more Limited by the number of devices that can be connected without complex management. degrading performance. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 84 42  STACK CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 85 STACK The location where the contents of the registers are temporarily stored is called the stack. Used by the CPU to store information from registers temporarily This is because there is limited number of register inside the microprocessor The two main registers to access the stack are SS (Stack Segment) and SP(Stack Pointer) registers. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 86 43  TYPES OF STACK There are TWO types of stacks: Hardware Stack A numbers of registers are set aside within the processor to serve as the stack location. ADVANTAGE: rapid access time. DISADVANTAGE: limited numbers of registers Software Stack An area inside the RAM for temporary storage. Therefore, need a special register in the CPU to hold address of the stack -> STACK POINTER REGISTER ADVANTAGES: almost unlimited size and can reside anywhere inside the memory. DISADVANTAGE: slow access time CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 87 STACK FUNCTIONS/USAGES When a subroutine is called. When an interrupt occurs. When stack instruction occurs. To store data when the most recently used data will also be the first needed. Efficient way of storing intermediate data values during complex calculations. CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 88 44  OPERATION OF STACK The stack address is built, one byte at a time (like the memory operations) Stack operates by Last In First Out (LIFO) The last byte put on the stack will be the first byte retrieved from the stack Examples of Operations: To store data onto the stack (PUSH AX) To retrieve data from the stack (POP AX) Last plate put in will be first plate out First plate put in will be last plate out CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 89 STACK POINTER The job of Stack Pointer (SP) is very critical when push and pop are performed. The SP points to the top of the stack (which is not empty). SP incremented when data is popped off the stack (removed from) SP is decremented when data is pushed onto the stack (put onto) CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 90 45  EXAMPLE 1: PUSHING ONTO STACK Assuming that SP = 1236h, AX = 24B6h, BX = 85C2h, DX = 5F93h Show the contents of the stack as each of the following instructions is executed PUSH AX PUSH BX PUSH DX CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 91 PUSHING ONTO STACK - ANSWER PUSH AX Before: SP = 1236h Operation: Decrement SP by 2, then store AX at the new SP location. SP: 1236h - 2 = 1234h SP 1234 B6 low byte of AX 1235 24 high byte of AX 1236 SP CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 92 46  PUSHING ONTO STACK - ANSWER PUSH BX Before: SP = 1234h Operation: Decrement SP by 2, then store BX at the new SP location. SP: 1234h - 2 = 1232h SP 1232 C2 low byte of BX 1233 85 high byte of BX 1234 B6 low byte of AX 1235 24 high byte of AX 1236 SP CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 93 PUSHING ONTO STACK - ANSWER PUSH DX Before: SP = 1232h Operation: Decrement SP by 2, then store DX at the new SP location. SP: 123Dh - 2 = 1230h SP 1230 93 low byte of DX 1231 5F high byte of DX 1232 C2 low byte of BX 1233 85 high byte of BX 1234 B6 low byte of AX 1235 24 high byte of AX 1236 SP Finally, SP is : 1230 CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 94 47  EXAMPLE 2: PUSHING ONTO STACK Given the assembly language instruction: MOV AX, 24B6h MOV BX, 85C2h MOV DX, 5F93h Draw a stack diagram starting at address 1236h after the instruction are executed. State the contents of AX, BX, DX PUSH AX PUSH BX PUSH DX CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 95 PUSHING ONTO STACK - ANSWER SP 1231 93 low byte of DX 1232 5F high byte of DX 1233 C2 low byte of BX 1234 85 high byte of BX 1235 B6 low byte of AX 1236 24 high byte of AX Finally, SP is : 1231 1237 SP CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 96 48  POPPING OFF STACK Given the following stack and SP = 18FA, show the contents of the stack and registers after executing the following instructions: POP CX SP 18FA 23 POP DX 18FB 14 POP BX 18FC 6B 18FD 2C 18FE 91 18FF F6 1900 25 ** Usually, the stack is build following the little-endian method CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 97 POPPING OFF STACK- ANSWER POP CX Before: SP = 18FAh Operation: Load word at address 18FAh – 18FBh into CX Increment SP by 2 after loading, SP = 18FA + 2 = 18FC, CX = 1423 18FA 23 18FB 14 SP 18FC 6B 18FD 2C 18FE 91 18FF F6 1900 25 CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 98 49  POPPING OFF STACK- ANSWER POP DX Before: SP = 18FCh Operation: Load word at address 18FCh – 18FDh into DX Increment SP by 2 after loading, SP = 18FC + 2 = 18FEh, DX = 2C6B 18FA 23 18FB 14 18FC 6B 18FD 2C SP 18FE 91 18FF F6 1900 25 CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 99 POPPING OFF STACK- ANSWER POP BX Before: SP = 18FEh Operation: Load word at address 18FEh – 18FFh into DX Increment SP by 2 after loading, SP = 18FE + 2 = 1900h, BX = F691 18FA 23 18FB 14 18FC 6B 18FD 2C 18FE 91 18FF F6 SP 1900 25 Finally, SP is : 1900 CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 100 50  ENDIAN ORDER Refers to the way computer stores the bytes of a multiple byte integer Two orders: (1) Little Endian (2) Big Endian Intel processor PCs are little endian machines, whereas Motorola processors (used in Macs) are big endian machines CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 101 LITTLE ENDIAN Low-order byte of number is stored in memory at the lowest address, & high- order byte at the highest address little end comes first Example: a 4-byte LongInt Byte3 Byte2 Byte1 Byte0 will be arranged in memory as follows: Base Address + 0 Byte0 Base Address + 1 Byte1 Base Address + 2 Byte2 Base Address + 3 Byte3 CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 102 51  BIG ENDIAN High-order byte of number is stored in memory at lowest address, & low- order byte at the highest address big end comes first Example: a 4-byte LongInt Byte3 Byte2 Byte1 Byte0 will be arranged in memory as follows: Base Address + 0 Byte3 Base Address + 1 Byte2 Base Address + 2 Byte1 Base Address + 3 Byte0 CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 103 ENDIAN ORDER Why should it matter to you? Most of the time it won’t, but if you try to read data files created on a machine that is of different endian nature from your machine, the bytes must be swapped to obtain same values on both machines Common file formats & their endian order:.psd >> big endian.bmp >> little endian.gif >> little endian.jpeg >> big endian CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 104 52  EXERCISE 1 Based on the instructions given below, draw an appropriate stack diagram, starting from address 2000: MOV AX, 1234h MOV BX, 9ABCh PUSH BX PUSH AX State the content of the stack pointer after the execution of the above instructions. Arrange the words in the stack using Big Endian Little Endian CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 105 EXERCISE 2 Given the content of registers and the byte that follows the PUSH instruction at the time interrupt occurs (address given in hexadecimal): AX : 1432h BX : A263h CX : 0BACAh DX : 0312h PC : 1003h Flag Register : 04h SP : 200Ch X X 1 1 0 1 0 1 AX BX CX DX PC FR CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 106 53  EXERCISE 2 (CONT.) Build a stack following the sequence of PC, AX, BX, CX, DX and flag register. Show the content of Stack Pointer Register after the stack building is finished. Why is stack needed when an interrupt occurs? CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 107 EXERCISE 3 CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 108 54  EXERCISE 4 CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 109 THANK YOU!!! CSC159 | COMPUTER ORGANIZATION | YUSNITA SOKMAN 110 55