SN74HC193-Q1 4-Bit Synchronous Up/Down Counter PDF

   

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       SCLS594A − NOVEMBER 2004 − REVISED APRIL 2008 D Qualified for Automotive Applications D Fully Synchronous in Count Modes D Wide Operating Voltage Range of 2 V to 6 V D Parallel Asynchronous Load for Modulo-N D Outputs Can Drive Up To 10 LSTTL Loads Count Lengths D Low Power Consumption, 80-µA Max ICC D Asynchronous Clear D Typical tpd = 20 ns D ±4-mA Output Drive at 5 V PW PACKAGE (TOP VIEW) D Low Input Current of 1 µA Max D Look-Ahead Circuitry Enhances Cascaded B 1 16 VCC Counters QB 2 15 A QA 3 14 CLR description/ordering information DOWN 4 13 BO UP 5 12 CO The SN74HC193 device is a 4-bit synchronous, QC 6 11 LOAD reversible, up/down binary counter. Synchronous QD 7 10 C operation is provided by having all flip-flops clocked GND 8 9 D simultaneously so that the outputs change simultaneously with each other when dictated by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP or DOWN). The direction of counting is determined by which count input is pulsed while the other count input is high. All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs. A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The clear function is independent of the count and LOAD inputs. This counter was designed to be cascaded without the need for external circuitry. The borrow (BO) output produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO) output produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counter then can be cascaded easily by feeding BO and CO to DOWN and UP, respectively, of the succeeding counter. ORDERING INFORMATION{ ORDERABLE TOP-SIDE TA PACKAGE‡ PART NUMBER MARKING −40°C to 125°C TSSOP − PW Reel of 2000 SN74HC193QPWRQ1 HC193Q −40°C to 85°C TSSOP − PW Reel of 2000 SN74HC193IPWRQ1 HC193I † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.    !"#$%! & '("")% $& ! *(+,'$%! -$%). Copyright  2008, Texas Instruments Incorporated "!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%& &%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&. POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1 
   

       SCLS594A − NOVEMBER 2004 − REVISED APRIL 2008 logic diagram (positive logic) 12 CO 13 BO 14 CLR 5 UP 4 DOWN S 11 LOAD R 15 A 3 S QA C1 1D R 1 B 2 S QB C1 1D R 10 C 6 S QC C1 1D R 9 D 7 S QD C1 1D R 2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 
   

       SCLS594A − NOVEMBER 2004 − REVISED APRIL 2008 typical clear, load, and count sequence The following sequence is illustrated below: 1. Clear outputs to 0 2. Load (preset) to binary 13 3. Count up to 14, 15, carry, 0, 1, and 2 4. Count down to 1, 0, borrow, 15, 14, and 13 CLR LOAD A B Data Inputs C D UP DOWN QA QB Data Outputs QC QD CO BO 0 13 14 15 0 1 2 1 0 15 14 13 Count Up Count Down Clear Preset NOTES: A. CLR overrides LOAD, data, and count inputs. B. When counting up, count-down input must be high; when counting down, count-up input must be high. POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3 
   

       SCLS594A − NOVEMBER 2004 − REVISED APRIL 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC.......................................................... −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1).................................... ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1)................................ ±20 mA Continuous output current, IO (VO = 0 to VCC).............................................. ±25 mA Continuous current through VCC or GND................................................... ±50 mA Package thermal impedance, θJA (see Note 2)............................................ 108°C/W Storage temperature range, Tstg................................................... −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN NOM MAX UNIT VCC Supply voltage 2 5 6 V VCC = 2 V 1.5 VIH High-level input voltage VCC = 4.5 V 3.15 V VCC = 6 V 4.2 VCC = 2 V 0.5 VIL Low-level input voltage VCC = 4.5 V 1.35 V VCC = 6 V 1.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 2 V 1000 ∆t/∆v‡ Input transition rise/fall time VCC = 4.5 V 500 ns VCC = 6 V 400 Q-suffix devices −40 125 TA Operating free-air temperature °C I-suffix devices −40 85 NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. 4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 
   

       SCLS594A − NOVEMBER 2004 − REVISED APRIL 2008 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = −40°C TA = −40°C TA = 25°C PARAMETER TEST CONDITIONS VCC TO 125°C TO 85°C UNIT MIN TYP MAX MIN MAX MIN MAX 2V 1.9 1.998 1.9 1.9 IOH = −20 µA 4.5 V 4.4 4.499 4.4 4.4 VOH VI = VIH or VIL 6V 5.9 5.999 5.9 5.9 V IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84 IOH = −5.2 mA 6V 5.48 5.8 5.2 5.34 2V 0.002 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 VOL VI = VIH or VIL 6V 0.001 0.1 0.1 0.1 V IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 IOL = 5.2 mA 6V 0.15 0.26 0.4 0.33 II VI = VCC or 0 6V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6V 8 160 80 µA Ci 2 V to 6 V 3 10 10 10 pF POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5 
   

       SCLS594A − NOVEMBER 2004 − REVISED APRIL 2008 timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = −40°C TA = −40°C TA = 25°C VCC TO 125°C TO 85°C UNIT MIN MAX MIN MAX MIN MAX 2V 4.2 2.8 3.3 fclock Clock frequency 4.5 V 21 14 17 MHz 6V 24 16 19 2V 120 180 150 CLR high 4.5 V 24 36 30 6V 21 31 26 2V 120 180 150 tw Pulse duration LOAD low 4.5 V 24 36 30 ns 6V 21 31 26 2V 120 180 150 UP or DOWN, high or low 4.5 V 24 36 30 6V 21 31 26 2V 110 165 140 Data before LOAD inactive 4.5 V 22 33 28 6V 19 28 24 2V 110 165 140 tsu Setup time CLR inactive before UP↑ or DOWN↓ 4.5 V 22 33 28 ns 6V 19 28 24 2V 110 165 140 LOAD inactive before UP↑ or DOWN↓ 4.5 V 22 33 28 6V 19 28 24 2V 5 5 5 th Hold time Data after LOAD inactive 4.5 V 5 5 5 ns 6V 5 5 5 6 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 
   

       SCLS594A − NOVEMBER 2004 − REVISED APRIL 2008 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) TA = −40°C TA = −40°C FROM TO TA = 25°C PARAMETER VCC TO 125°C TO 85°C UNIT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX 2V 4.2 8 2.8 3.3 fmax 4.5 V 21 55 14 17 MHz 6V 24 60 16 19 2V 75 165 250 205 UP CO 4.5 V 24 33 50 41 6V 20 28 43 35 2V 75 165 250 205 DOWN BO 4.5 V 24 33 50 41 6V 20 28 43 35 tpd ns 2V 190 250 375 315 UP or DOWN Any Q 4.5 V 40 50 75 63 6V 35 43 64 54 2V 190 260 390 325 LOAD Any Q 4.5 V 40 52 78 65 6V 35 44 66 55 2V 170 240 360 300 tPHL CLR Any Q 4.5 V 36 48 72 60 ns 6V 31 41 61 51 2V 38 75 110 95 tt Any 4.5 V 8 15 22 19 ns 6V 6 14 19 17 operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load 50 pF POST OFFICE BOX 655303 DALLAS, TEXAS 75265 7 
   

       SCLS594A − NOVEMBER 2004 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION VCC High-Level 50% 50% Pulse From Output Test 0V Under Test Point tw CL = 50 pF VCC (see Note A) Low-Level 50% 50% Pulse 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS VCC Input 50% 50% 0V tPLH tPHL VCC In-Phase VOH Reference 50% 90% 90% Output 50% 50% Input 10% 10% 0V VOL tr tf tsu th tPHL tPLH Data VCC VOH 90% 90% Out-of-Phase 90% 90% Input 50% 50% 50% 50% 10% 10% 0 V Output 10% 10% VOL tr tf tf tr VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 DALLAS, TEXAS 75265  PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SN74HC193QPWRG4Q1 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HC193Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of