PRELIM CPE-MSS PDF

CPE-MSS PRELIM Input 2 is in phase with output1 and out-off Topic 1: Differential Amplifiers...

CPE-MSS PRELIM Input 2 is in phase with output1 and out-off Topic 1: Differential Amplifiers phase with output2 Stages Diff Amp -> Voltage Amp -> Push-pull Amp -> Load Double-Ended Differential Input Input -> Sensor -> Controller -> Actuator -> Output When two opposite-polarity (out-of-phase) signals are Differential Amplifier - amplifier that produces applied to the inputs. outputs that are a function of the difference between two input voltages. - Essential component of operational amplifier Most Common Op-Amp – LM741 Common Mode Inputs Two basic modes of operation condition where two signal Single-Ended Differential Input voltages of the same phase, Differential-Ended Differential Input frequency, and amplitude are applied to the two inputs Basic Differential Amplifier Diff-amp has two inputs and two outputs Common Mode Rejection If both inputs are grounded (0 V), Cancelling out of two signal common to both emitters are at -0.7V inputs of the differential amplifier 𝐼𝐸1 = 𝐼𝐸2 Cancelling of unwanted signal (noise) appears Both emitter currents combine commonly on both diff-amp inputs through 𝑅𝐸 𝐼 𝐼𝐸1 = 𝐼𝐸2 = 𝑅𝐸 𝐼𝑅𝐸 𝑉 −𝑉 = 𝐸 𝐸𝐸 Common Mode Rejection Ratio (CMRR) 2 2 𝑅𝐸 Desired signals appear on only one input or with Approximating IC = IE. opposite polarities on both input lines. 𝑰𝑹𝑬 𝑰𝑪𝟏 = 𝑰𝑪𝟐 = Unwanted signals (noise) appearing with the 𝟐 same polarity on both input lines are essentially Since both collector currents and both collector cancelled by the diff-amp and do not appear on resistors are equal the outputs. 𝑽𝑪𝟏 = 𝑽𝑪𝟐 = 𝑽𝑪𝑪 − 𝑰𝑪𝟏 𝑹𝑪𝟏 The measure of an amplifier’s ability to reject If input 2 is left grounded, and a positive voltage common-mode signals is applied to input 1, IC1 increases and the 𝐴𝑣(𝑑) - differential gain emitter voltage increases to: 𝐴𝑐𝑚 - common mode gain 𝑨𝒗(𝒅) 𝑽𝑬 = 𝑽𝑩 − 𝟎. 𝟕𝑽 𝑪𝑴𝑹𝑹 = VBE of Q2 reduces causing IC2 to decrease. 𝑨𝒄𝒎 decrease in IC2 increases VC2 , and Increase in IC2 Ideally, infinite decreases VC2. infinite Av(d), and zero Acm Reverse result when input 1 is grounded and a Practically, very high positive bias voltage is applied to input 2. 𝑨𝒗(𝒅) 𝑪𝑴𝑹𝑹 = 𝟐𝟎 𝐥𝐨𝐠 ( ) 𝑨𝒄𝒎 Single-Ended Differential Input When one input is The higher the differential gain with respect to the grounded and the signal common-mode gain, the better the performance of voltage is applied only to the diff-amp in terms of rejection of common-mode the other input signals. This suggests that a good measure of the diff- amp’s performance in rejecting unwanted common- Input 1 is in phase with mode signals is the ratio of the differential voltage gain output2 and out-off phase with output1 Av(d ) to the common-mode gain, Acm. Lower - For a given value of differential gain, does a Op-amps have both voltage and current limitations. higher CMRR result in a higher or lower common-mode Peak-to-peak output voltage, for example, is usually gain? limited to slightly less than the two supply voltages. Output current is also limited by internal restrictions Example: CMRR such as power dissipation and component ratings. 1. A certain diff-amp has a differential voltage gain of 2000 and a common-mode gain of 0.2. Internal Block Diagram of an Op-Amp Determine the CMRR and express it in decibels. Differential Amplifier Input stage, provide voltage amplification of the difference between the two inputs Topic 2: Operational Amplifiers Eliminate noise Operational Amplifiers Voltage Amplifier Stage used primarily to perform mathematical Second stage that provides additional voltage operations such as addition, subtraction, gain integration, and differentiation Usually class A amplifier Conceptualized in 1947, used vacuum tubes - most common for higher linearity First IC opamp (702) developed by Fairchild Semiconductor in 1964 Linearity - the ability of the amplifier to produce signals Followed by 709, then by 741 (industry standard) that are accurate copies of the input. Output Stage For impedance matching Equivalent of Thevenin Voltage Matching the output impedance to the load resistance Typically class B amplifier - higher efficiency but lower linearity The higher the efficiency rating of an amplifier, the Ideal Op-Amp Vs. Practical Op-Amp more power the amp will make and the less heat it will generate overall. Input Signal Modes Differential Mode Single-ended Differential Mode Ideal Op-Amp Practical Op-Amp Infinite Voltage Gain Very high Voltage Gain Infinite Bandwidth Very high Bandwidth One signal is applied to an input with the other Infinite Input Very high Input input grounded Impedance Impedance Zero Output Very low Output Impedance Impedance Double-ended Differential Mode Input Offset Voltage (VOS) Two opposite-polarity signals are applied to the inputs The differential dc voltage required between the inputs to force the output to zero volts (2mV or less) Common Mode Two signal voltages of the Input offset voltage drift - change occurs in the input same phase, frequency, offset voltage for each degree change in temperature and amplitude are applied to the two inputs Input Bias Current (IBIAS) DC current required by the Common-Mode Rejection inputs of the amplifier to When equal input signals are applied to both properly operate the first inputs, they tend to cancel, resulting in a zero stage. output voltage Op-Amp Parameters Input Impedance (ZIN) Common-mode Rejection Ratio (CMRR) Differential Input Impedance measure of an amplifier’s ability to reject - Total resistance between the inverting and the common-mode signals noninverting inputs 𝑨𝒐𝒍 𝑨𝒐𝒍 Common-mode Input Impedance 𝑪𝑴𝑹𝑹 = = 𝟐𝟎 𝐥𝐨𝐠 ( ) 𝑨𝒄𝒎 𝑨𝒄𝒎 - Resistance between each input and ground and Aol = Open-loop gain, Acm = common-mode gain is measured by determining the change in bias Ideal op-amp has infinite CMRR current for a given change in common-mode Practical op-amp has very high CMRR input voltage Example: CMRR Input Offset Current (IOS) 2. An op-amp has open-loop differential voltage Difference of the gain Aol = 90 dB and a common-mode gain Acm input bias currents, = –6 dB. Determine CMRR in decibels and in expressed as an magnitude. absolute value 𝐼𝑂𝑆 = |𝐼1 − 𝐼2 | 𝑉𝑂𝑆 = (𝐼1 − 𝐼2 )𝑅𝑖𝑛 = 𝐼𝑂𝑆 𝑅𝑖𝑛 𝑉𝑂𝑈𝑇(𝑒𝑟𝑟𝑜𝑟) = 𝐴𝑉 𝐼𝑂𝑆 𝑅𝑖𝑛 Output Impedance (ZOUT) Resistance viewed from the output terminal of the op-amp Maximum Output Voltage Swing (VO(p-p)) The limits of the peak-to- peak output signal which is Slew Rate (SR) - The maximum rate of change of the ideally ±VCC and +VCC for output voltage in response to a step input voltage. some. ∆𝑽𝒐𝒖𝒕 𝑺𝑹 = ∆𝒕 Example: Slew Rate Why use negative feedback? 1. The output voltage of a certain op-amp appears as shown in the figure in response to a step input. Aol of op-amp is very high (100k) Determine the slew rate. Extremely small input voltage drives the op- amp into a saturated output state (even the offset voltage) The closed-loop voltage gain (Acl) can be reduced and controlled so that the op-amp can function as a linear amplifier Frequency Response - The voltage gain of an op-amp is limited by the junction capacitances. Op-Amps with Negative Feedback CLOSED-LOOP GAIN (Acl) Voltage gain of an op-amp with external feedback An op-amp and an external negative feedback circuit that connects the output to the inverting input. Noise Specification Non-Inverting Amplifier Noise - unwanted signal that affects the quality of a desired signal Pink Noise or 1/f Noise o Noise Non-Ideal 𝐀𝐨𝐥 Ideal 𝐀𝐨𝐥 below critical noise frequency 𝑽𝒐𝒖𝒕 𝑨𝒐𝒍 𝑹𝒇 = 𝑨𝒄𝒍 = 𝟏 + o A noise 𝑽𝒊𝒏 (𝟏 + 𝜷𝑨𝒐𝒍 ) 𝑹𝒊 inversely proportional to frequency Acl is not at all dependent on the op-amps open-loop White Noise gain under the condition AolB>>1, where B is the o Above a critical noise frequency, the feedback factor. noise becomes flat and is spread out equally across the frequency spectrum. Example: Non-Inverting Op-Amp Topic 3: Operational Amplifiers (P2) Determine the closed-loop voltage gain of the amplifier. Negative Feedback - Process whereby a portion of the output voltage of an amplifier is returned to the input with a phase angle that opposes the input signal. Voltage Follower Impedances of the Noninverting Amplifier 𝑨𝒄𝒍 = 𝟏 Input Impedance The straight feedback 𝒁𝒊𝒏(𝒄𝒍) = (𝟏 + 𝑨𝒐𝒍 𝜷)𝒁𝒊𝒏 connection has a voltage gain of 1. Zin(cl) > Zin Very high input Zin of the noninverting impedance and its very low amplifier configuration output impedance, ideal with negative feedback is much greater than the buffer amplifier internal Zin of the op-amp itself. Inverting Amplifier Output Impedance 𝒁𝒐𝒖𝒕 𝒁𝒐𝒖𝒕 (𝒄𝒍) = 𝟏 + 𝑨𝒐𝒍 𝜷 Zout(cl) Zin(NI) Output Impedance 𝒁𝒐𝒖𝒕 𝒁𝒐𝒖𝒕 (𝒄𝒍) = 𝟏 + 𝑨𝒐𝒍 Zout(VF) < Zout(NI) Example: Voltage Follower Op-Amp Bandwidth Limitation If the op-amp below is used in a voltage-follower configuration, determine the input and output impedances. The op-amp has Zin = 2MΩ, Zout = 75 Ω, and Aol = 200,000 Bode plot of an op-amp Midrange Open-loop Gain Gain from zero frequency (dc) up to critical frequency of an op-amp Critical Frequency Frequency where the gain is 3dB less than the midrange value 3 dB Open-Loop Bandwidth Impedances of the Inverting Amplifier Frequency range where gain is 3dB less than midrange gain Input Impedance Unity-Gain Frequency (fT) 𝒁𝒊𝒏(𝑰) = 𝑹𝒊 Unity Gain Bandwidth Frequency at which unity gain occurs. Output Impedance 𝒁𝒐𝒖𝒕 Gain-Versus-Frequency Analysis 𝒁𝒐𝒖𝒕(𝑰) = Low-Pass Filter 𝟏 + 𝑨𝒐𝒍 𝜷 Zout is decreased by the negative feedback, practically 𝑽𝒐𝒖𝒕 𝟏 zero so can be connected to any load impedance = 𝑽𝒊𝒏 𝒇𝟐 Example: Inverting Op-Amp √𝟏 + ⁄ 𝟐 𝒇𝒄 Find the values of the input and output impedances. 𝟏 Also, determine the closed-loop voltage gain. The op- 𝒇𝒄 = 𝟐𝝅𝑹𝑪 amp has the following parameters: Aol = 50,000; Zin = 4M f = operating frequency Ω; and Zout = 50 Ω. fc = cut-off frequency Op-amp represented by voltage element (Aol(mid)) and single RC lag circuit 𝑽𝒐𝒖𝒕 𝑨𝒐𝒍(𝒎𝒊𝒅) = 𝑽𝒊𝒏 𝒇𝟐 √𝟏 + ⁄ 𝟐 𝒇𝒄 Topic 4: Frequency Response Frequency Response indicates how the voltage gain changes with frequency. Example: Gain-Frequency Analysis Determine Aol of f. Assume fc(ol) = Phase Response indicates how the phase shift 100 Hz and Aol(mid) = 100,000. between the input and output signal changes with a) f = 10 Hz frequency. Phase Shift - Propagation delay between the input Example: Phase Shift signal and the output signal Low-Pass Filter Lag Circuit 𝑹 𝒇 𝜽 = −𝒕𝒂𝒏−𝟏 ( ) = −𝒕𝒂𝒏−𝟏 ( ) 𝑿𝒄 𝒇𝒄 θ = phase shift Negative indicates the output lags the input Example: Phase Shift Calculate the phase shift for an RC lag circuit with f= 10Hz, and then plot the curve of phase shift versus frequency. Assume fc=100 Hz. 𝟏𝟎𝑯𝒛 𝜽 = −𝒕𝒂𝒏−𝟏 ( ) = −𝟓. 𝟕𝟏° 𝟏𝟎𝟎𝑯𝒛 Overall Frequency Response Frequency Response of Op-amp Op-amps consist of two or more cascaded amplifier stages Three-stages op-amp Effect of Negative Feedback on Bandwidth Closed-loop gain compared to open- loop gain Overall Open-loop Frequency Response Closed-loop critical frequency 𝒇𝒄 (𝒄𝒍) = 𝒇𝒄 (𝒐𝒍) (𝟏 + 𝜷𝑨𝒐𝒍 (𝒎𝒊𝒅) ) 𝑨𝒗𝟏 𝑨𝒗𝟐 𝑨𝒗𝟑 𝑨𝒗,𝒕𝒐𝒕 = × × Closed-loop Bandwidth 𝒇𝟐 𝒇𝟐 𝒇𝟐 𝑩𝑾(𝒄𝒍) = 𝑩𝑾(𝒐𝒍) (𝟏 + 𝜷𝑨𝒐𝒍 (𝒎𝒊𝒅) ) √𝟏 + ⁄ 𝟐 √𝟏 + ⁄ 𝟐 √𝟏 + ⁄ 𝟐 𝒇𝒄𝟏 𝒇𝒄𝟐 𝒇𝒄𝟑 𝛽 is feedback factor This expression shows that the closed-loop critical Overall Phase Response frequency, fc(cl), is higher than the open-loop critical 𝒇 𝒇 𝒇 frequency 𝜽𝒕𝒐𝒕 = −𝒕𝒂𝒏−𝟏 ( ) −𝒕𝒂𝒏−𝟏 ( ) −𝒕𝒂𝒏−𝟏 ( ) 𝒇𝒄𝟏 𝒇𝒄𝟐 𝒇𝒄𝟑 Example: Effect of Negative Feedback on BW and fc A certain amplifier has an open-loop midrange gain of 150,000 and an open-loop 3 dB bandwidth of 200 Hz. The attenuation (B) of the feedback loop is 0.002. What is the closed-loop bandwidth? Gain Bandwidth Product (GBW) Example: Comparator Always equal to the frequency at which the op-amps Draw the output signal showing its proper relationship open-loop gain is unity (0dB). to the input signal. Assume maximum output levels of 𝑮𝑩𝑾 = 𝑨𝒄𝒍 𝒇𝒄(𝒄𝒍) = 𝑨𝒐𝒍 𝒇𝒄(𝒐𝒍) = 𝒇𝑻 the comparator are ±14V. An increase in closed-loop gain causes a decrease in the bandwidth and vice versa, such that the product of gain and bandwidth is a constant. (for a fixed roll-off rate) Example: Effect of Negative Feedback on BW and fc Determine the bandwidth of the amplifier. It has an open-loop gain of 100 dB and a unity-gain bandwidth (fT) of 3 MHz. Effects of Input Noise on Comparator Operation NOISE - Unwanted voltage fluctuations Noise becomes superimposed on the input/output voltage When a low frequency signal superimposed with noise is an input to a zero-level detector Topic 5: Basic Op-Amp Circuits Reducing Noise Effects with Hysteresis Noise causes erratic output voltage in op-amp when Comparator is a specialized op-amp circuit that input voltage hover around the reference voltage. compares two input voltages and produces an output HYSTERESIS - higher reference level (UTP or upper that is always at either one of two states, indicating the trigger point) when input voltage goes from a lower to greater or less than relationship between the inputs. higher value than when it goes from a higher to a lower Often used to interface analog and digital value (LTP or lower trigger point) circuits. When the output is Op-amp as comparator. at the maximum Zero-Level Detection positive voltage Circuit to determine and the input when an input voltage exceeds a exceeds UTP, the certain value. output switches to High open-loop gain the maximum drives the op-amp into saturation negative voltage even for a small difference voltage between the two inputs. Two level hysteresis Inverting terminal – grounded (zero level) Non-inverting connected to a resistive voltage divider Non-inverting terminal – input signal Inverting input – input signal If the opamp is capable to provide the output Assume vout is at positive maximum (Voutmax) Input voltage must be exceed Vutp to change the output NonZero Level Detection from +Voutmax to -Voutmax Modified zero-level When the output is at detector. the maximum Detects positive and negative voltages by negative voltage and connecting fixed voltage the input goes below source to the inverting input. LTP, the output Battery reference switches back to the Voltage divider reference maximum positive Zener diode sets reference voltage voltage  Device triggers only Turning the zener around limits the output once when UTP or voltage in the opposite direction LTP is reached; thus, Two zener diodes limit the output voltage to there is immunity to zener voltage plus the forward voltage drop noise that is riding on (0.7V) the input signal SCHMITT TRIGGER - Comparator with built in Example: Comparator Determine the output voltage waveform hysteresis 𝑽𝑯𝒀𝑺 = 𝑽𝑼𝑻𝑷 − 𝑽𝑳𝑻𝑷 Input must exceed UTP to trigger low Input must fall below LTP to trigger high Example: Comparator (UTP & LTP) Determine the upper and lower trigger points for the comparator circuit below. Assume that +Vout(max) = +5V and –Vout(max) = -5V. Comparator Application 1. Analog-to-Digital Conversion - common interfacing process often used when a linear analog system must provide inputs to a digital system 2. Simultaneous or Flash ADC - Also called parallel ADC Output Bounding - Limiting the output range of a – formed of a series of comparators, each comparator to a value less than that provided by the one comparing the input signal to a saturated op-amp. unique reference voltage. The Bounded at comparator outputs connect to the a positive inputs of a priority encoder circuit, value which then produces a binary output. Example: ADC Flash ADC Limit the output voltage to the zener voltage in one direction and to forward diode voltage drop in the other Anode in inverting is at virtual ground. When output is high, limited to a zener voltage When output switches negative, zener acts as regular diode – limited forward biased voltage 0.7V Bounded at a negative value Summing Amplifiers has two or more inputs, and its Double- bounded output voltage is proportional to the negative of the Comparator algebraic sum of its input voltages  Two-input inverting Example: Averaging Amplifier summing amplifier Show that the amplifier below produces an output whose magnitude is the mathematical average of the 𝑰𝑻 = 𝑰𝟏 + 𝑰𝟐 input voltages. 𝑽𝑰𝑵𝟏 𝑽𝑰𝑵𝟐 𝑽𝑶𝑼𝑻 = −(𝑰𝟏 + 𝑰𝟐 )𝑹𝒇 = − ( + ) 𝑹𝒇 𝑹𝟏 𝑹𝟐 If three resistors are equal (R1 = R2 = RF = R) 𝑽𝑶𝑼𝑻 = −(𝑽𝑰𝑵𝟏 + 𝑽𝑰𝑵𝟐 ) Summing amplifier with n inputs All resistors are equal in value Scaling Amplifier 𝑽𝑶𝑼𝑻 = −(𝑽𝑰𝑵𝟏 + 𝑽𝑰𝑵𝟐 + 𝑽𝑰𝑵𝟑 + ⋯ + 𝑽𝑰𝑵𝒏 ) A different weight can be assigned to each input of a summing amplifier by simply adjusting the values of the Example: Summing Amplifier input resistors. Determine the output voltage of the summing amplifier 𝑹𝒇 𝑹𝒇 𝑹𝒇 𝑽𝑶𝑼𝑻 = −( 𝑽𝑰𝑵𝟏 + 𝑽𝑰𝑵𝟐 + ⋯ + 𝑽𝑰𝑵𝒏) 𝑅1 𝑅2 𝑅𝑛 Example: Scaling Amplifier Determine the weight of each input voltage for the scaling adder and find the output voltage. Summing Amplifier with Gain Greater Than Unity When Rf is larger than the input resistors, the amplifier has a gain of Rf /R, where R is the value of each equal- value input resistor. 𝑹𝒇 𝑽𝑶𝑼𝑻 = − (𝑽𝑰𝑵𝟏 + 𝑽𝑰𝑵𝟐 + ⋯ + 𝑽𝑰𝑵𝒏) 𝑹 Summing Amplifier Application Example: Summing Amplifier Digital-to-Analog Conversion Determine the output voltage of the summing amplifier - important interface process for converting digital signals to analog (linear) signals DAC can be implemented using scaling adder - Just need to set the values of the resistors properly Example: Binary-Weighted Resistor DAC Averaging Amplifier Summing amplifier that produces the mathematical average of the input voltages by setting the ratio Rf/R equal to the reciprocal of the number of inputs. 𝑹𝒇 1 = 𝑅 𝑛