Multiple-Choice Reviewer PDF

Multiple-Choice Reviewer Part 1: Theoretical Questions 1.​ What is the main function of an encoder? ○​ A) Convert 2^n input lines into n output lines. ○​ B) Convert n input lines into 2^n output lines. ○​ C) Decode binary input into decimal output. ○​...

Multiple-Choice Reviewer Part 1: Theoretical Questions 1.​ What is the main function of an encoder? ○​ A) Convert 2^n input lines into n output lines. ○​ B) Convert n input lines into 2^n output lines. ○​ C) Decode binary input into decimal output. ○​ D) Manage memory address assignments. 2.​ What output will a 3-to-8 decoder produce if the inputs are all 0 (S0=0, S1=0, S2=0)? ○​ A) D1 ○​ B) D0 ○​ C) D7 ○​ D) None 3.​ In the Von Neumann architecture, what does the ALU primarily handle? ○​ A) Input/output operations ○​ B) Memory management ○​ C) Arithmetic and logical operations ○​ D) Control signal generation 4.​ Which of the following is NOT a feature of the Von Neumann architecture? ○​ A) Sequential processing of instructions ○​ B) Separate storage for data and instructions ○​ C) Shared pathway for data and instructions ○​ D) Use of a control unit and ALU in the CPU 5.​ What does the system bus consist of? ○​ A) Address Bus, Data Bus, Control Bus ○​ B) Memory, CPU, I/O devices ○​ C) ALU, Control Unit, Registers ○​ D) Data Encoder, Decoder, Selector 6.​ What determines the memory capacity of a processor? ○​ A) Data Bus size ○​ B) Control Bus signals ○​ C) Number of address bus bits ○​ D) Input-output lines 7.​ How many inputs does a 4-to-16 decoder require? ○​ A) 4 ○​ B) 16 ○​ C) 8 ○​ D 8.​ What is the purpose of the control bus in a system bus? ○​ A) Transfer actual data between the CPU and memory ○​ B) Manage and coordinate operations like read and write  ○​ C) Determine memory locations ○​ D) Select specific memory chips 9.​ For an 8-bit microprocessor, what does the size of the address bus determine? ○​ A) Number of instructions ○​ B) Number of memory locations it can access ○​ C) Number of I/O devices supported ○​ D) Number of ALU operations 10.​What is the size of the MPU capacity of the Intel 8086 processor? ○​ A) 64 KB ○​ B) 1 MB ○​ C) 512 KB ○​ D) 128 KB 11.​What happens when all inputs of a decoder are set to logic 1? ○​ A) All outputs are activated ○​ B) No outputs are activated ○​ C) The highest output is activated ○​ D) The lowest output is activated 12.​In memory address computation, what does the term 'chip selector' refer to? ○​ A) The entire address bus ○​ B) The portion of the address bus used to select a specific memory chip ○​ C) The data bus lines ○​ D) The decoder outputs 13.​How is memory divided in the Von Neumann architecture? ○​ A) Between input and output devices ○​ B) Into program memory and data memory ○​ C) Into ALU and control units ○​ D) Into address and data buses 14.​Which device converts binary input into a unique decimal output? ○​ A) Encoder ○​ B) Decoder ○​ C) Multiplexer ○​ D) Arithmetic Logic Unit 15.​Which of the following is an example of a 3-bit address line's memory capacity? ○​ A) 8 addresses ○​ B) 16 addresses ○​ C) 4 addresses ○​ D) 32 addresses 16.​Which memory address assignment method stores sequential memory in a single chip? ○​ A) Interleaving ○​ B) Sequential mapping ○​ C) Direct mapping ○​ D) Decoder mapping 17.​How many memory locations are available with a 12-bit address bus?  ○​ A) 1024 ○​ B) 2048 ○​ C) 4096 ○​ D) 8192 18.​What determines the number of outputs in a decoder? ○​ A) Number of inputs squared ○​ B) Logarithm of the number of inputs ○​ C) 2 raised to the number of inputs ○​ D) Number of outputs times two 19.​Which of these is NOT part of the system bus? ○​ A) Address Bus ○​ B) Decoder Bus ○​ C) Data Bus ○​ D) Control Bus 20.​In an 8-memory chip system with a 3-to-8 decoder, what does the decoder do? ○​ A) Selects the active chip based on address inputs ○​ B) Transfers data between chips ○​ C) Stores all memory addresses ○​ D) Converts binary input to decimal output Part 2: Problem-Solving Questions 21.​How many unique memory locations can a processor with a 16-bit address bus access? ○​ A) 2152^{15}215 ○​ B) 2162^{16}216 ○​ C) 282^{8}28 ○​ D) 161616 22.​A processor has 20 address lines. What is the maximum memory capacity it can handle? ○​ A) 512 KB ○​ B) 1 MB ○​ C) 2 MB ○​ D) 4 MB 23.​If an Intel 8080 processor has 16 address lines, what is its memory capacity? ○​ A) 64 KB ○​ B) 128 KB ○​ C) 256 KB ○​ D) 32 KB 24.​Given a memory chip with a capacity of 1 KB, how many address lines are required? ○​ A) 8 ○​ B) 10  ○​ C) 12 ○​ D) 16 25.​If a decoder has 4 inputs, how many output lines does it produce? ○​ A) 4 ○​ B) 8 ○​ C) 16 ○​ D) 32 26.​A processor has a 24-bit address bus. What is the total addressable memory in bytes? ○​ A) 216 ○​ B) 220 ○​ C) 224 ○​ D) 282 27.​A decoder receives inputs 0110. Which output line is active in a 4-to-16 decoder? ○​ A) D6 ○​ B) D4 ○​ C) D8 ○​ D) D3 28.​How many bits are required in the address bus to access 256 KB of memory? ○​ A) 16 ○​ B) 18 ○​ C) 20 ○​ D) 24 29.​A memory chip is organized as 1,024 locations, each storing 4 bits. What is its capacity in bytes? ○​ A) 1 KB ○​ B) 2 KB ○​ C) 512 bytes ○​ D) 4 KB 30.​If a processor uses a 3-to-8 decoder, what range of memory chips can it access? ○​ A) 0-4 ○​ B) 0-7 ○​ C) 0-15 ○​ D) 1-8 31.​Compute the number of address lines needed for a 512 MB memory capacity. ○​ A) 29 ○​ B) 28 ○​ C) 30 ○​ D) 32 32.​A system uses a 5-to-32 decoder. How many memory blocks can it address? ○​ A) 16 ○​ B) 32 ○​ C) 64  ○​ D) 128 33.​What is the base-2 logarithm of 1,048,576 bytes, and what does it represent? ○​ A) 10; number of memory chips ○​ B) 20; number of address lines ○​ C) 16; memory capacity ○​ D) 24; processor speed 34.​If a decoder maps a 4-bit input, what is the hexadecimal range of addresses it can generate? ○​ A) 0x0 to 0xF ○​ B) 0x0 to 0xFF ○​ C) 0x0 to 0xFFFF ○​ D) 0x0 to 0xFFF 35.​An address bus has 32 lines. Compute the addressable memory capacity. ○​ A) 220 ○​ B) 224 ○​ C) 232 ○​ D) 216 Part 2: Problem-Solving Questions (continued) 36.​If a processor has an 18-bit address bus, how many unique memory locations can it address? ○​ A) 216 ○​ B) 218 ○​ C) 220 ○​ D) 18 37.​A memory chip has a capacity of 4 KB. How many address lines are required to access all its locations? ○​ A) 10 ○​ B) 11 ○​ C) 12 ○​ D) 13 38.​A system with a 3-to-8 decoder uses 8 memory chips, each with 256 bytes of capacity. What is the total memory capacity of the system? ○​ A) 1 KB ○​ B) 2 KB ○​ C) 4 KB ○​ D) 8 KB 39.​A decoder receives input 1100. In a 4-to-16 decoder, which output line will be active? ○​ A) D8 ○​ B) D10 ○​ C) D12  ○​ D) D14 40.​If a memory chip stores 1,024 locations of 8 bits each, what is its total capacity in bytes? ○​ A) 512 bytes ○​ B) 1 KB ○​ C) 2 KB ○​ D) 4 KB 41.​A memory system has 64 KB of memory with a 16-bit address bus. What is the range of memory addresses in hexadecimal? ○​ A) 0x0000 to 0xFFFF ○​ B) 0x0000 to 0x7FFF ○​ C) 0x0000 to 0x1FFFF ○​ D) 0x0000 to 0x3FFF 42.​If a decoder has 5 inputs, how many unique outputs does it generate? ○​ A) 16 ○​ B) 32 ○​ C) 64 ○​ D) 128 43.​A processor has 24 address lines. Compute the memory capacity in megabytes. ○​ A) 16 MB ○​ B) 32 MB ○​ C) 64 MB ○​ D) 128 MB 44.​Given a 10-bit address bus, what is the range of memory addresses (in decimal) it can access? ○​ A) 0 to 512 ○​ B) 0 to 1023 ○​ C) 0 to 2047 ○​ D) 0 to 4095 45.​A system uses a 4-to-16 decoder to divide memory into 16 blocks. Each block has 4 KB capacity. What is the total memory capacity? ○​ A) 64 KB ○​ B) 32 KB ○​ C) 16 KB ○​ D) 128 KB 46.​If a processor with a 20-bit address bus accesses 1 MB of memory, how many memory locations are in each kilobyte? ○​ A) 256 ○​ B) 512 ○​ C) 1,024 ○​ D) 2,048 47.​An 8-bit microprocessor uses a 16-bit address bus with a 1 KB memory chip. How many memory chips are required to fill the address space? ○​ A) 16  ○​ B) 32 ○​ C) 64 ○​ D) 128 48.​A decoder maps memory for 8 chips, each with 2 KB capacity. What is the highest addressable memory location in hexadecimal? ○​ A) 0x1FFF ○​ B) 0x3FFF ○​ C) 0x7FFF ○​ D) 0xFFFF 49.​If a processor has 15 address lines, what is the maximum memory capacity it can access in bytes? ○​ A) 16 KB ○​ B) 32 KB ○​ C) 64 KB ○​ D) 128 KB 50.​A memory system uses a 3-to-8 decoder. If the input to the decoder is 011, which memory chip will be selected? ○​ A) Chip 2 ○​ B) Chip 3 ○​ C) Chip 6 ○​ D) Chip 7