Computer Architecture Quiz - Part 1 & 2

An encoder converts a set of n input lines into 2^n output lines. It essentially translates a signal into a binary code.

When all inputs of a 3-to-8 decoder are 0 (S0=0, S1=0, S2=0), the output D0 will be activated, representing the binary code 000, which is decimal 0.

The Arithmetic Logic Unit (ALU) is the core of the CPU, responsible for performing all mathematical calculations (addition, subtraction, etc.) and logical operations (AND, OR, NOT) within a computer system.

The Von Neumann architecture uses a single shared bus to transfer both data and instructions to the CPU, allowing for more efficient use of memory and bandwidth.

The system bus acts as the central communication channel connecting the CPU, memory, and input/output devices. It consists of the address bus, data bus, and control bus.

The number of bits in the address bus determines the maximum memory locations a processor can access. For instance, a 16-bit address bus allows addressing 2^16 (65,536) memory locations.

A 4-to-16 decoder requires 4 inputs to select one of 16 possible outputs. It uses the input combination to activate a specific output.

The control bus transmits control signals between the CPU and other components. These signals manage and synchronize operations like memory read/write, data transfer, and device operations.

The portion of the address bus used to select a specific memory chip. This is used to activate a particular memory chip when the processor wants to access data.

A memory organization where both instructions and data share the same address space. This means that instructions and data can be stored at the same memory locations.

A circuit that converts a binary input into a unique decimal output. It has a specific output for each combination of input bits.

The method of assigning sequential memory locations to a single memory chip. It helps to read and write memory locations in a contiguous manner.

The number of unique memory locations that a processor can access. It is determined by the number of address lines. (2 raised to the power of the number of address lines).

A circuit that has multiple inputs but only one output. The output will correspond to the input line that is selected by a control signal.

A system of assigning memory addresses to multiple memory chips, where the addresses are distributed across the chips in a non-consecutive manner.

The number of outputs in a decoder is determined by raising 2 to the power of the number of inputs.

A decoder with 4 inputs can generate 2^4 = 16 unique output lines. Each output line corresponds to a specific address within the address space.

A 24-bit address bus can address 2^24 memory locations, which can be expressed in bytes. The total addressable memory is therefore 2^24 bytes, or 16,777,216 bytes.

The decoder's input 0110 corresponds to output line D6, as each input combination activates a specific, unique output line.

To address 256 KB (256 * 1024 bytes) of memory, 18 address lines are required. 2^18 = 262,144, which is slightly larger than 256,000 (256 KB).

The memory chip has a capacity of 1,024 * 4 bits = 4,096 bits. Converting to bytes, 4,096 bits / 8 bits/byte = 512 bytes.

A 3-to-8 decoder can select one out of eight memory chips. It addresses a range of memory chips with 2^3 = 8 possible combinations.

512 MB equals 512 * 1024 * 1024 bytes. To find the number of address lines, determine the power of 2 that is closest to this value. 2^29 is the nearest power of 2, so 29 address lines are needed.

A 5-to-32 decoder has 2^5 = 32 outputs, which can address 32 memory blocks. Each output line corresponds to a separate block of memory.

A 4-to-16 decoder has 16 unique outputs, represented by D0 to D15. The output line that will be active depends on the input value. Each input bit represents a specific weight in the output address. For the input 1100, the output address is calculated: 18 + 14 + 02 + 01 = 12. Therefore, for input 1100, the D12 output line will be active.

A memory chip with 1,024 (2^10) locations of 8 bits each has a total capacity of 1 KB (Kilobyte). This is because 1 KB = 1024 bytes, and each location is 8 bits, which is equivalent to 1 byte.

A memory system with 64 KB (2^16 bytes) of memory and a 16-bit address bus can access all the memory locations using the addresses ranging from 0x0000 to 0xFFFF. This is because 16 bits allow for 2^16 = 65,536 unique addresses, which covers the entire 64 KB memory space.

A decoder with 5 inputs can generate 2^5 = 32 unique outputs. This is calculated by raising 2 to the power of the number of inputs.

A processor having 24 address lines can access a maximum memory capacity of 2^24 bytes, which equals 16 MB (Megabytes). Each address line represents 1 bit in the address. Therefore, 24 address lines provide 2^24=16,777,216 unique memory locations. This equates to 16 MB, as 1 MB = 1,048,576 bytes.

A 10-bit address bus can access a range of 2^10 = 1024 memory addresses. This means the memory addresses range from 0 to 1023.

A 4-to-16 decoder divides memory into 16 blocks. Each block has 4 KB memory capacity. Therefore, the total memory capacity is 16 blocks * 4 KB/block = 64 KB.

A processor with a 20-bit address bus accesses 1 MB (2^20 bytes) of memory. Therefore, each kilobyte (1024 bytes) has 2^10 = 1024 memory locations. This is because each 10-bit address within a kilobyte can access a unique location.