Assembly Language Programming and Interrupts

**[Module II]** **[Assembly language programming and interrupts]** Assembly Language is a low level language. The instruction in assembly language is known as mnemonics. Eg: **MOV A,B** In this MOV means opcode, A,B means operand. **[Addressing modes]** Various methods of accessing the data ar...

**[Module II]** **[Assembly language programming and interrupts]** Assembly Language is a low level language. The instruction in assembly language is known as mnemonics. Eg: **MOV A,B** In this MOV means opcode, A,B means operand. **[Addressing modes]** Various methods of accessing the data are called addressing modes.8051 addressing modes are classified as follows: **1)Immediate addressing mode** In this addressing mode the data is provided as a part of instruction itself. In other words data immediately follows the instruction. Eg: **MOV A,\#30H** **ADD A,\#83H** **2)Register addressing mode** In this addressing mode the register will hold the data. one of the 8 general registers(R~0~ to R~7~) can be used and specified as the operand. Eg**: MOV A,R~0~** **ADD A,R~6~** **3)Direct addressing mode** In this addressing mode in which the data operand is in the RAM location (00-7FH) and the address of the data operand is given in the instruction is known as direct addressing mode. Eg**: MOV R~1,~42H** **4)Indirect addressing mode** The indirect addressing mode uses a register to hold the actual address that will be in data movement.Register R~0~ and R~1~ and DPTR are the only registers that can be used as data pointer. Eg**: MOV A,\@R~0~** **ADD A,\@R~1~** **5)Indexed addressing mode** In indexed addressing , either the PC or the DPTR is used to hold the base address and A is used to hold the offset address. The sum of base address and offset address forms effective address. Eg: **MOV A,\@A+DPTR** **MOV A,\@A+PC** **[Instruction set of 8051]** The 8051 instruction set is divided in to four functional groups. **1.Data transfer** **2.Arithmetic** **3.Logic** **4.Control transfer** **1. Data transfer** Data transfer operations are divided in to 3 classes. **a)General purpose transfer** - **MOV :** move a bit or byte from source operand to destination operand. - **PUSH** : PUSH increments the stack pointer (SP) register and then transfers a byte from the source operand to the stack location currently addressed by SP. - **POP** : Transfer a byte operand from the stack location addressed by SP to the destination operand and then decrements SP. **b) Accumulator -- specific transfer** - **XCH** : Exchanges the byte source operand with register A. - **MOVX**: Performs a byte move between external data memory and accumulator.The external address can be specified by the DPTR or the R~0~ and R~1~ register. - **MOVC**: Moves a byte from program memory to the accumulator. **c) Address -- object transfer** **MOV DPTR ,\#data** loads 16 bits of immediate data in to a pair of destination DPH and DPL. **2. Arithmetic** The 8051 has 4 basic mathematical operations. **a)Addition** - **INC** : Adds one to the source operand and puts the result in the operand - **ADD**: adds A to the source operand and return the result to A - **ADDC** : Adds A and the source operand then adds one if CY is set and put the result in A. **b)subtraction** - **SUBB:** Subtracts the second source operand from the first operand. Subtracts one if cy is set and returns the result to A. - **DEC**: Subtracts one from the source operand and returns the result to the operand. **c)Multiplication** - **MUL**: It perform an unsigned multiplication of the A register by the B register returning a double byte result. **d) Division** - **DIV:** It performs an unsigned division of the A register by the B register and returns the integer quotient to A and returns the fractional reminder to the B register.CY, AC,OV,P flags of PSW is set during DIV operation performs. - **3. Logic** The 8051 performs basic logic operations on both bit and byte operands. **a)Single -- Operand operations** - **CLR:** Set A or any directly addressable bit to 0. - **SETB:** Sets any directly addressable bit to 1. - **CPL:** It is used to compliment the contents of the A register without effecting any flag or any directly addressable bit location. - **Rotate** instructions a**) RR- RRA**: This instruction is rotate right the accumulator. 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- b**) RL- RLA** : Rotate left the accumulator. 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- c\) **RRC- RRCA**: Rotate rights through the carry. 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- d\) **RLC- RLCA** : Rotate left through the carry. 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- e\) **SWAP** -- **Swap A** -- Swap the upper and lower nibble of A. **b) Two -- Operand operations** - **ANL:** Performs bit wise logical AND of two source operands and returns the result to the location of the first operand. - **ORL:** Performs bit wise logical OR of two source operand and returns the result to the location of the first operand. - **XRL :** Performs bit wise logical XOR of two source operands and returns the result to the location of the first operand. **4. Control Transfer** - **ACALL and LCALL:** Push the address of the next instruction on to the stack and then transfer control to the target address. - **RET:** Transfer control to the return address saved on the stack by a previous call operation. - **AJMP, L JMP and SJMP:** Transfer control to the target operand. - **JMP@ A+ DPTR:** Performs a jump relative to the DPTR register - **JZ:** Performs a jump if the accumulator is zero. - **JNZ:** Performs a jump if the accumulator is not zero. - **JC:** Performs a jump if the carry flag is set. - **JNC:** Performs a jump if the carry flag is not set. - **DJNZ:** Decrements the source operand and returns the result to the operand. - **CJNE:** Compares the first operand to the second operand and perform a jump if they are not equal. c\) **Interrupt Returns** **RET 1:** Transfer control as does RET, but additionally enables interrupts of the current priority level. **[Interrupts in 8051]** An interrupt is an external or internal event that disturbs the microcontroller to inform that a device needs its service. The program which is associated with the interrupt is called Interrupt Service Routine or Interrupt handler(ISR).Upon receiving interrupt signal the microcontroller, finish current instruction and saves the program counter on stack. Upon executing the RET1 instruction the microcontroller returns to the place where it was interrupted. After RET1 ends pop program counter from stack. **[Steps involved in interrupt processing of 8051]** 1\) It completes the execution of the current instruction. 2\) Program counter is pushed on to the stack. 3\) Jumps to a fixed location in memory depend on type of interrupt. 4\) Starts to execute the interrupt service routine until RET1. 5\) Upon executing the RET1 the microcontroller returns to the place where it was interrupted. 6\) Pop program counter from stack. 7\) Interrupt status is restored to its original value. **[Types of interrupt]** 8051 has 6 sources of interrupt. 1\) **Reset:** When the reset pin is activated, the 8051 jumps to address location 0000H. 2\) **Timer0 Overflow Interrupts(TF0):** When a timer/counter overflows, the corresponding timer flag TF0 in TCON register is set to 1. (vector addresses:-000BH and 001BH) 3\) **Timer1 Overflow Interrupts(TF1):** When a timer/counter overflows, the corresponding timer flag TF1 in TCON register is set to 1. (vector addresses:-000BH and 001BH) 4\) **External Interrupts0(INTO):** Inputs on these pins can set the interrupt flags IE0 in the TCON register to 1.( vector addresses:-0003H and 0013H) 5\) **External Interrupts1(INTO):-** Inputs on these pins can set the interrupt flags IE1 in the TCON register to 1. ( vector addresses:-0003H and 0013H) 6\) **Serial Port Interrupt(R1/T1):** If a data byte is received, an interrupt bit R1 is set to 1 in the SCON register. When a data byte has been transmitted an interrupt bit T1 is set to 1 in SCON register. ( vector addresses:-0023H) **[Interrupt Priority]** Interrupt Priority Register(IP) determine any interrupt is to have a high or low priority. Bits set to 1 give the accompanying interrupt a high priority, a 0 assigns a low priority can interrupt another interrupt with a lower priority, the lower priority interrupt continues after the higher is finished. If two interrupts with the same priority occur at the same time, then they have the following ranking. Interrupt Source Type Vector address Priority --------------------- ---------- ---------------- ---------- External Interrupt0 External 0003 Highest Timer 0 Interrupt Internal 000B External Interrupt1 External 0013 Timer1 Interrupt Internal 001B Serial Interrupt Internal 0023 Lowest **[Interrupt Enable Register(IE)]** EA \- ET2 ES ET1 EX1 ET0 EX0 ---- ---- ----- ---- ----- ----- ----- ----- 7 6 5 4 3 2 1 0 +-----------------------+-----------------------+-----------------------+ | Bit | Symbol | Function | +=======================+=======================+=======================+ | 7 | EA | Enable interrupt bit. | | | | | | | | Set to 0-Enable all | | | | interrupts. | | | | | | | | Set to 1-Disable all | | | | interrupts. | +-----------------------+-----------------------+-----------------------+ | 6 | \- | Not implemented | +-----------------------+-----------------------+-----------------------+ | 5 | ET2 | Reserved for future | | | | use. | +-----------------------+-----------------------+-----------------------+ | 4 | ES | Enable serial port | | | | interrupt. | | | | | | | | Set to 0-Enable | | | | Serial port | | | | interrupt. | | | | | | | | Set to 1-Disable | | | | Serial port | | | | interrupt. | +-----------------------+-----------------------+-----------------------+ | 3 | ET1 | Enable Timer1 | | | | overflow interrupt. | | | | | | | | Set to 0-Enable | | | | Timer1 overflow | | | | interrupt. | | | | | | | | Set to 1-Disable | | | | Timer1 overflow | | | | interrupt. | +-----------------------+-----------------------+-----------------------+ | 2 | EX1 | Enable External | | | | interrupt1 interrupt. | | | | | | | | Set to 0-Enable | | | | External interrupt1 | | | | interrupt. | | | | | | | | Set to 1-Disable | | | | External interrupt1 | | | | interrupt | +-----------------------+-----------------------+-----------------------+ | 1 | ET0 | Enable Timer0 | | | | overflow interrupt. | | | | | | | | Set to 0-Enable | | | | Timer0 overflow | | | | interrupt. | | | | | | | | Set to 1-Disable | | | | Timer0overflow | | | | interrupt. | +-----------------------+-----------------------+-----------------------+ | 0 | EX0 | Enable External | | | | interrupt1 interrupt. | | | | | | | | Set to 0-Enable | | | | External interrupt0 | | | | interrupt. | | | | | | | | Set to 1-Disable | | | | External interrupt0 | | | | interrupt | +-----------------------+-----------------------+-----------------------+ **[Interrupt Priority Register((IP)]** +--------+--------+--------+--------+--------+--------+--------+--------+ | \- | \- | PT2 | PS | PT1 | PX1 | PT0 | PX0 | +========+========+========+========+========+========+========+========+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +--------+--------+--------+--------+--------+--------+--------+--------+ | Bit | Symbol | Functi | | | | | | | | | on | | | | | | +--------+--------+--------+--------+--------+--------+--------+--------+ | 7 | \- | Not | | | | | | | | | implem | | | | | | | | | ented. | | | | | | +--------+--------+--------+--------+--------+--------+--------+--------+ | 6 | \- | Not | | | | | | | | | implem | | | | | | | | | ented. | | | | | | +--------+--------+--------+--------+--------+--------+--------+--------+ | 5 | PT2 | Reserv | | | | | | | | | ed | | | | | | | | | for | | | | | | | | | future | | | | | | | | | use. | | | | | | +--------+--------+--------+--------+--------+--------+--------+--------+ | 4 | PS | Priori | | | | | | | | | ty | | | | | | | | | of | | | | | | | | | serial | | | | | | | | | port | | | | | | | | | interr | | | | | | | | | upt. | | | | | | | | | | | | | | | | | | Set/Cl | | | | | | | | | eared | | | | | | | | | by | | | | | | | | | progra | | | | | | | | | m. | | | | | | +--------+--------+--------+--------+--------+--------+--------+--------+ | 3 | PT1 | Priori | | | | | | | | | ty | | | | | | | | | of | | | | | | | | | Timer1 | | | | | | | | | overfl | | | | | | | | | ow | | | | | | | | | interr | | | | | | | | | upt. | | | | | | | | | | | | | | | | | | Set/Cl | | | | | | | | | eared | | | | | | | | | by | | | | | | | | | progra | | | | | | | | | m. | | | | | | +--------+--------+--------+--------+--------+--------+--------+--------+ | 2 | PX1 | Priori | | | | | | | | | ty | | | | | | | | | of | | | | | | | | | Extern | | | | | | | | | al | | | | | | | | | interr | | | | | | | | | upt1 | | | | | | | | | interr | | | | | | | | | upt. | | | | | | | | | | | | | | | | | | Set/Cl | | | | | | | | | eared | | | | | | | | | by | | | | | | | | | progra | | | | | | | | | m. | | | | | | +--------+--------+--------+--------+--------+--------+--------+--------+ | 1 | PT0 | Priori | | | | | | | | | ty | | | | | | | | | of | | | | | | | | | Timer0 | | | | | | | | | overfl | | | | | | | | | ow | | | | | | | | | interr | | | | | | | | | upt. | | | | | | | | | | | | | | | | | | Set/Cl | | | | | | | | | eared | | | | | | | | | by | | | | | | | | | progra | | | | | | | | | m. | | | | | | +--------+--------+--------+--------+--------+--------+--------+--------+ | 0 | PX0 | Priori | | | | | | | | | ty | | | | | | | | | of | | | | | | | | | Extern | | | | | | | | | al | | | | | | | | | interr | | | | | | | | | upt0 | | | | | | | | | interr | | | | | | | | | upt. | | | | | | | | | | | | | | | | | | Set/Cl | | | | | | | | | eared | | | | | | | | | by | | | | | | | | | progra | | | | | | | | | m. | | | | | | +--------+--------+--------+--------+--------+--------+--------+--------+ [Extra questions] 1.How interrupts are enabled and disabled Ans: Interrupts can be **enabled or disabled by setting bits of the IE register** **2.Mention assembler directives** Ans:The following are the widely used 8051 assembler directives. **ORG (origin):** The ORG directive is used to indicate the starting address. **EQU and SET** :EQU and SET directives assign numerical value or register name to the specified symbol name. **DB (DEFINE BYTE)** :The DB directive is used to define an 8 bit data **END**: The END directive signals the end of the assembly module. **3.Distinguish between Level and Edge triggered Interrupts** **Level-Triggered:** A level-triggered interrupt module always generates an interrupt whenever the level of the interrupt source is asserted. **Edge-Triggered:** An edge-triggered interrupt module generates an interrupt only when it detects an asserting edge of the interrupt source A level-triggered interrupt module generates an interrupt when and while the interrupt source is asserted. If the interrupt source is still asserted when the firmware interrupt handler acks the interrupt, the interrupt module will regenerate the interrupt, causing the interrupt handler to be invoked again. This is not good if the interrupt source can potentially stay asserted for a long time. On the other hand, edge-triggered interrupt modules can be acked immediately, no matter how the interrupt source behaves. The type of the interrupt source does not matter. It can be a pulse, a firmware-clearable signal, or some external signal that eventually is cleared somehow.