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Assembly Language Programming and Interrupts

• Assembly Language is a low-level language where instructions are known as mnemonics (e.g., MOV A,B).
• In "MOV A,B", MOV represents the opcode, and A,B represents the operand.

Addressing Modes

• Addressing modes provide various methods for accessing data
• The 8051 addressing modes are classified as follows:

Immediate Addressing Mode

• The data is part of the instruction itself.
• For example: MOV A,#30H; ADD A,#83H

Register Addressing Mode

• A register holds the data where one of the 8 general registers (R0 to R7) is used as the operand.
• For example: MOV A,R0; ADD A,R1

Direct Addressing Mode

• The operand is in the RAM location (00-7FH), and its address is given in the instruction.
• For example: MOV R1,42H

Indirect Addressing Mode

• A register holds the actual address used for data movement.
• Registers R0, R1, and DPTR can be used as data pointers.
• For example: MOV A,@R0; ADD A, @R1

Indexed Addressing Mode

• Either the PC or the DPTR holds the base address, and A holds the offset address.
• The sum of the base and offset addresses forms the effective address.
• For example: MOV A,@A+DPTR; MOV A,@A+PC

Instruction Set of 8051

• The instruction set is divided into four functional groups:
  • Data Transfer
  • Arithmetic
  • Logic
  • Control Transfer

Data Transfer Operations

• Divided into three classes:

General Purpose Transfer

• MOV: Moves a bit or byte from source to destination operand.
• PUSH: Increments the stack pointer (SP) and transfers a byte from the source operand to the stack location addressed by SP.
• POP: Transfers a byte operand from the stack location addressed by SP to the destination operand and then decrements SP.

Accumulator-Specific Transfer

• XCH: Exchanges the byte source operand with register A.
• MOVX: Moves a byte between external data memory and the accumulator, where the external address can be specified by DPTR, R0, or R1.
• MOVC: Moves a byte from program memory to the accumulator.

Address-Object Transfer

• MOV DPTR,#data: Loads 16 bits of immediate data into a pair of destination DPH and DPL.

Arithmetic Operations

• The 8051 has four basic mathematical operations:

Addition

• INC: Adds one to the source operand and puts the result in the operand.
• ADD: Adds A to the source operand and returns the result to A.
• ADDC: Adds A and the source operand, then adds one if CY is set, and puts the result in A.

Subtraction

• SUBB: Subtracts the second source operand from the first operand and subtracts one if CY is set; returns the result to A.
• DEC: Subtracts one from the source operand and returns the result to the operand.

Multiplication

• MUL: Performs an unsigned multiplication of the A register by the B register, returning a double-byte result.

Division

• DIV: Performs an unsigned division of the A register by the B register, and returns the integer quotient to A and the fractional remainder to the B register
• CY, AC, OV, and P flags of PSW are set during the DIV operation.

Logic Operations

• The 8051 performs basic logic operations on both bit and byte operands:

Single-Operand Operations

• CLR: Sets A or any directly addressable bit to 0.
• SETB: Sets any directly addressable bit to 1.
• CPL: Complements the contents of the A register without affecting any flag or directly addressable bit location.

Rotate Instructions

• RR/RRA: Rotates right the accumulator.
• RL/RLA: Rotates left the accumulator.
• RRC/RRCA: Rotates right through the carry.
• RLC/RLCA: Rotates left through the carry.

Two-Operand Operations

• ANL: Performs bitwise logical AND of two source operands and returns the result to the location of the first operand.
• ORL: Performs bitwise logical OR of two source operands and returns the result to the location of the first operand.
• XRL: Performs bitwise logical XOR of two source operands and returns the result to the location of the first operand.
• SWAP: Swaps the upper and lower nibble of A.

Control Transfer

• There are three classes of control transfer operations:

Unconditional Calls, Returns, and Jumps

• Transfer control from the current value of the PC to the target address
• Direct and indirect transfers are supported.
• ACALL and LCALL: Push the address of the next instruction onto the stack and transfer control to the target address.
• RET: Transfers control to the return address saved on the stack by a previous call operation.
• AJMP, LJMP, and SJMP: Transfer control to the target operand.
• JMP@A+DPTR: Jumps relative to the DPTR register.

Conditional Jumps

• Perform a jump based on a specific condition.
• JZ: Jumps if the accumulator is zero.
• JNZ: Jumps if the accumulator is not zero.
• JC: Jumps if the carry flag is set.
• JNC: Jumps if the carry flag is not set.
• DJNZ: Decrements the source operand and jumps if the result is not zero.
• CJNE: Compares the first operand to the second operand and jumps if they are not equal.

Interrupt Returns

• RETI: Transfers control and enables interrupts of the current priority level.

Interrupts in 8051

• An interrupt is an external or internal event that informs the microcontroller that a device needs service.
• The program associated with the interrupt is called the Interrupt Service Routine (ISR) or Interrupt Handler.
• Upon receiving an interrupt signal, the microcontroller finishes the current instruction and saves the program counter on the stack.
• Upon executing RETI, the microcontroller returns to the place where it was interrupted and pops the program counter from the stack.

Steps Involved in Interrupt Processing

• Completes the execution of the current instruction.
• The program counter is pushed onto the stack.
• Jumps to a fixed memory location depending on the type of interrupt.
• Starts the interrupt service routine until RETI.
• Upon executing RETI, the microcontroller returns to where it was interrupted.
• Pop program counter from stack.
• Interrupt status is restored to its original value.

Types of Interrupt

• The 8051 has 6 sources of interrupt:
  • Reset: When activated, the 8051 jumps to address location 0000H.
  • Timer0 Overflow Interrupt (TF0): When a timer/counter overflows, the corresponding timer flag TF0 in the TCON register is set to 1 (vector addresses: 000BH and 001BH).
  • Timer1 Overflow Interrupt (TF1): When a timer/counter overflows, the corresponding timer flag TF1 in the TCON register is set to 1 (vector addresses: 000BH and 001BH).
  • External Interrupt 0 (INT0): Inputs on these pins can set the interrupt flag IE0 in the TCON register to 1 (vector addresses: 0003H and 0013H).
  • External Interrupt 1 (INT1): Inputs on these pins can set the interrupt flag IE1 in the TCON register to 1 (vector addresses: 0003H and 0013H).
  • Serial Port Interrupt (RI/TI): If a data byte is received, an interrupt bit RI is set to 1 in the SCON register; when a data byte is transmitted, the interrupt bit TI is set to 1 in the SCON register (vector address: 0023H).

Interrupt Priority

• The Interrupt Priority Register (IP) determines if an interrupt has a high or low priority.
• Bits set to 1 give the interrupt a high priority; a 0 gives it a low priority.
• A high-priority interrupt can interrupt a low-priority interrupt.
• If two interrupts have the same priority, they are ranked as follows:
  • External Interrupt 0 (Highest)
  • Timer 0 Interrupt
  • External Interrupt 1
  • Timer 1 Interrupt
  • Serial Interrupt (Lowest)

Interrupt Enable Register (IE)

• EA (Bit 7): Enable interrupt bit; set to 0 to enable all interrupts, set to 1 to disable all interrupts.
  • ET2 (Bit 6): Reserved for future use.
  • ES (Bit 4): Enable serial port interrupt; set to 0 to enable, set to 1 to disable.
  • ET1 (Bit 3): Enable Timer1 overflow interrupt; set to 0 to enable, set to 1 to disable.
  • EX1 (Bit 2): Enable External interrupt 1 interrupt; set to 0 to enable, set to 1 to disable.
  • ET0 (Bit 1): Enable Timer0 overflow interrupt; set to 0 to enable, set to 1 to disable.
  • EX0 (Bit 0): Enable External interrupt 0 interrupt; set to 0 to enable, set to 1 to disable.

Interrupt Priority Register (IP)

• PT2 (Bit 5): Reserved for future use.
• PS (Bit 4): Priority of serial port interrupt; set/cleared by the program.
• PT1 (Bit 3): Priority of Timer1 overflow interrupt; set/cleared by the program.
• PX1 (Bit 2): Priority of External interrupt 1 interrupt; set/cleared by the program.
• PT0 (Bit 1): Priority of Timer0 overflow interrupt; set/cleared by the program.
• PX0 (Bit 0): Priority of External interrupt 0 interrupt; set/cleared by the program.

Interrupts - Additional Information

• Interrupts can be enabled or disabled by setting bits of the IE register

Assembler Directives

• Common 8051 assembler directives include:
  • ORG (origin): Indicates the starting address.
  • EQU and SET: Assign numerical value or register name to a specified symbol name.
  • DB (DEFINE BYTE): Used to define an 8-bit data value.
  • END: Signals the end of the assembly module.

Level-Triggered Interrupts

• A level-triggered interrupt module always generates an interrupt whenever the level of the interrupt source is asserted.

Edge-Triggered Interrupts

• An edge-triggered interrupt module generates an interrupt only when an asserting edge of the interrupt source is detected.