Logic Circuits Midterm PDF

Multiplexers Rev 1.3  Multiplexers A multiplexer (MUX) is a device that takes data from several different sources and transmits them over a single line to the same destination. Multiplexers consist of several data inputs or channels, a number of select lines...

Multiplexers Rev 1.3  Multiplexers A multiplexer (MUX) is a device that takes data from several different sources and transmits them over a single line to the same destination. Multiplexers consist of several data inputs or channels, a number of select lines to determine which input channel is to be transmitted and a single output channel. Channels may have a capacity of just a single bit or a number of bits. The number of bits determines the channel width. 2  The Multiplexer A B 4 Channel x 1-Bit Z Input Channels Output Channel C Multiplexer D Z=AS1S0+BS1S0+CS1S0+DS1S0 S1 S 0 Channel Select 3 Multiplexer 00 4 Multiplexer 01 1 0 5 Multiplexer 01 1 0 6 Multiplexer 01 1 0 7 Multiplexer 00 8  Multiplexer 11 2009 Peter Lindorff 9  Multiplexer 11 2009 Peter Lindorff 10  Multiplexer 11 2009 Peter Lindorff 11  Multiplexer 11 2009 Peter Lindorff 12  Multiplexers A B C D 8 Channel Z0 E x 1-Bit F G H S2 S1 S0 Z0=AS2S1S0+ BS2S1S0+ CS2S1S0+ DS2S1S0+ ES2S1S0+ FS2S1S0 + GS2S1S0 + HS2S1S0 13  Multiplexers A1 A0 Z1=A1S1S0+ B1S1S0+ C1S1S0+ B1 D1S1S0 B0 4 Channel Z1 x 2-Bit Z0 C1 C0 Z0=A0S1S0+ B0S1S0+ C0S1S0+ D0S1S0 D1 D0 Channel width is 2 bits S1 S0 14  Multiplexers A3 A0 Z3=A3S1S0+ B3S1S0+ C3S1S0+ D3S1S0 B3 Z2=A2S1S0+ B2S1S0+ C2S1S0+ B0 4 Channel Z3 D2S1S0 x 4-Bit Z0 Z1=A1S1S0+ B1S1S0+ C1S1S0+ C3 D1S1S0 C0 Z0=A0S1S0+ B0S1S0+ C0S1S0+ D0S1S0 D3 D0 Channel width is 4 bits S1 S0 15  Problems Name the following Multiplexers: Z3 – Z 0 2009 16  Solutions Name the following Multiplexers: 2 Chan 4 Chan 8 Chan X 1-Bit X 1-Bit X 1-Bit 2 Chan 2 Chan 4 Chan Z3 – Z 0 X 2-Bit X 4-Bit X 4-Bit 17  Problems Write the Boolean expressions for the multiplexers of the previous problems. Assume inputs are labelled as A, B, C, ….. Assume outputs are labelled as Z ….. Assume channel select inputs are labelled S ….. 18  Solutions Writing the Boolean expressions for the output Z 2 Chan X 1-Bit Z=AS0+BS0 4 Chan Z=AS1S0+BS1S0+CS1S0+DS1S0 X 1-Bit 19  Solutions Writing the Boolean expression for the output Z 8 Chan X 1-Bit Z = AS2S1S0+BS2S1S0+CS2S1S0+DS2S1S0+ ES2S1S0+FS2S1S0+GS2S1S0+HS2S1S0 20  Solutions Writing the Boolean expressions for the output Z 2 Chan Z1=A1S0+B1S0 X 2-Bit Z0=A0S0+B0S0 Z3=A3S0+B3S0 2 Chan Z2=A2S0+B2S0 X 4-Bit Z1=A1S0+B1S0 Z0=A0S0+B0S0 21  Solutions Writing the Boolean expression for the output Z Z3=A3S1S0+B3S1S0+C3S1S0+D3S1S0 Z2=A2S1S0+B2S1S0+C2S1S0+D2S1S0 4 Chan Z3 – Z 0 X 4-Bit Z1=A1S1S0+B1S1S0+C1S1S0+D1S1S0 Z0=A0S1S0+B0S1S0+C0S1S0+D0S1S0 22  A Little Circuitry A0 Z0 B0 2 Channel x 1-Bit Multiplexer Z=AS0+BS0 SO 23 4 Channel x 1-Bit Multiplexer A0 B0 Z0 C0 D0 S1 SO Z0=A0S1S0+B0S1S0+C0S1S0+D0S1S0 24 2 Channel x 2-Bit Multiplexer A0 Z0=A0S0+B0S0 B0 A1 Z1=A1S0+B1S0 B1 SO 25 Active Low or Active High Outputs Commercial multiplexers are available with active low or active high outputs. Some devices have both active low and active high output levels available. 26  2 Channel x 1-Bit Multiplexer with Active Low and Active High Outputs A0 Z0 B0 Z0 SO 27 Practical Multiplexers also have an Enable Input A0 Z0 B0 Z0 EN SO 28 Multiplexer with an Active low Enable A0 B0 Z0 4 Channel C0 X 1-Bit Multiplexer Z0 D0 EN S 1S 0 29  Applications Multiplexing of Displays Allows the use of a single, seven segment decoder driver to be shared by a number of different seven segment displays. Logic Function Generation Can be used to implement Sum of Products logic functions in a single device. Parallel to Serial Conversion 30 Display Multiplexing Logic (Simplified) Common Anode Displays +VDD 4 Seven Channel Segment X 4-Bit Decoder Multiplex Driver er 1 of 4 Decoder Channel/Display Select Decoder has only one output active at a time. 31  Display Multiplexing Logic +VDD Common Anode Displays 4 Seven Channel Segment X 4-Bit Decoder Multiplex Driver er Current Limiting Resistors 0 0 1 of 4 0 1 Decoder 1 0 1 1 Channel/Display Select Decoder has only one output active at a time. 32 The Light Emitting Diode (LED) VDD Anode Cathode RLimit Symbol Denotes Electron Current Flow 33 The Light Emitting Diode (LED) IFWD LED *Typical Colour VFWD Red 1.7V 20mA Yellow 2.2V Green 2.2V Blue 5.0V Symbol Amber 2.0V 1.7V VFWD Note: VFWD depends on the LED type and is usually quoted @ a particular IFWD. 34 The Common Anode 7-Segment LED Display Display LED Layout Internal Connections Common Anodes Cathodes 35  Logic Function Generation Implementing the three variable function using an 8 Channel x 1-Bit multiplexer.: Example: Z=Σm(1,2,5,7,) Remember the minterm list indicates the row in the truth table where Z is true. 36 Implementing Z=Σm(1,2,5,7,) +5V 0 1 2 8 3 Channel 4 Z = ABC+ABC+ABC+ABC X 1-Bit 5 Mux 6 7 EN ABC Note: Input variables connected to channel select inputs. 37 Using a multiplexer implement the following functions: 1. fABC = Σm(0, 1 ,3, 6) 2. Z = ABC+ABC+ABC 3. fABCD = Σm(0, 1, 8, 9, 10, 11, 15) 4. X = ABCD+ABCD+ABCD+ABCD+ABCD 38 Implementing Z=Σm(0,1,3,6) +5V 0 1 2 8 3 Channel 4 Z = ABC+ABC+ABC+ABC X 1-Bit 5 Mux 6 7 EN ABC 39 Implementing Z = ABC+ABC+ABC +5V 0 1 2 8 3 Channel 4 Z = ABC+ABC+ABC X 1-Bit 5 Mux 6 7 EN ABC 40 Implementing: Z=Σm(0,1,8,9,10,11,15) +5V 0 1 2 3 4 16 5 6 Channel 7 8 Z = ABCD+ABCD+ABCD+ABCD+ 9 X 1-Bit 10 11 Mux 12 13 ABCD+ABCD+ABCD 14 15 EN ABCD 41 Implementing: Z=Σm(7,9,13,14,15) +5V 0 1 2 3 4 16 5 6 Channel 7 8 Z = ABCD+ABCD+ABCD+ABCD+ 9 X 1-Bit 10 11 Mux 12 13 ABCD 14 15 EN ABCD 42  Parallel to Serial Conversion Register Register 1 1 1 1 0 0 Parallel Data 1 Serial Data DeM 1 Parallel Data Input Mux Output 0 ux 0 0 0 1 1 1 1 Synchronised 43 Commercial Multiplexers 44  Complementary Outputs 8 Channel x 1-bit Mux 45  74151 Function Table 2009 Peter Lindorff 46  Active High Enable 74150 Active Low Output Buffered Inputs 16 Channel X 1-Bit Mux Next slide for detail 47  1 74150 Input 2 Buffering 3 4 5 6 7 Without Input Buffering each Input Pin would represent 9 Unit Loads. 8 9 48  74150 Input Buffering 2009 Peter Lindorff 49  74150 Function Table 2009 Peter Lindorff 50 That’s All Folks! That’s All Folks! Now playing: Emperor Waltz 2009 Peter Lindorff 51 DIGITAL SYSTEMS TCE1111 OTHER COMBINATIONAL LOGIC CIRCUITS WEEK 7 AND WEEK 8 (LECTURE 2 OF 3) DECODERS ENCODERS 1 DIGITAL SYSTEMS TCE1111 DECODER A decoder is a logic circuit that accepts a set of inputs that represents a binary number and activates only the output that corresponds to the input number. In other words, a decoder circuit looks at its inputs, determines which binary number is present there, and activates the one output that corresponds to that number ; all other outputs remain inactive 2 DIGITAL SYSTEMS TCE1111 In its general form, a decoder has N input lines to handle N bits and form one to 2 N output lines to indicate the presence o one or more N-bit combinations. The basic binary function An AND gate can be used as the basic decoding element because it produces a HIGH output only when all inputs are HIGH Refer next slide for example 3 DIGITAL SYSTEMS TCE1111 Decoding logic for the binary code 1001 with an active-HIGH output. 4 DIGITAL SYSTEMS TCE1111 General decoder diagram # There are 2N possible input combinations, from A0 to AN−1. For each of these input combinations only one of the M outputs will be active HIGH (1), all the other outputs are LOW (0). 5 DIGITAL SYSTEMS TCE1111 If an active-LOW output (74138, one of the output will low and the rest will be high) is required for each decoded number, the entire decoder can be implemented with 1. NAND gates 2. Inverters If an active-HIGH output (74139, one of the output will high and the rest will be low) is required for each decoded number, the entire decoder can be implemented with AND gates Inverters 6 DIGITAL SYSTEMS TCE1111 2-to-4-Line Decoder (with Enable input)-Active LOW output (1)... 7 DIGITAL SYSTEMS TCE1111 2-to-4-Line Decoder (with Enable input)-Active LOW output (2) The circuit operates with complemented outputs and a complement enable input. The decoder is enabled when E is equal to 0. Only one output can be equal to 0 at any given time, all other outputs are equal to 1. The output whose value is equal to 0 represents the minterm selected by inputs A and B The circuit is disabled when E is equal to 1. 8 DIGITAL SYSTEMS TCE1111 3-8 line decoder (active-HIGH) 9 DIGITAL SYSTEMS TCE1111 This decoder can be referred to in several ways. It can be called a 3-line-to- 8-line decoder, because it has three input lines and eight output lines. It could also be called a binary-octal decoder or converters because it takes a three bit binary input code and activates the one of the eight outputs corresponding to that code. It is also referred to as a 1-of-8 decoder, because only 1 of the 8 outputs is activated at one time. 10 DIGITAL SYSTEMS TCE1111 Logic diagram of 74138 (Example of a 3−Bit Decoder) 11 DIGITAL SYSTEMS TCE1111 Truth table of 74138 (Example of a 3− 8 Bit Decoder) active-LOW 12 DIGITAL SYSTEMS TCE1111 74138 (Example of a 3− 8 Bit Decoder) There is an enable function on this device, a LOW level on each input E’1, and E’2, and a HIGH level on input E3, is required in order to make the enable gate output HIGH. The enable is connected to an input of each NAND gate in the decoder, so it must be HIGH for the NAND gate to be enabled. If the enable gate is not activated then all eight decoder outputs will be HIGH regardless of the states of the three input variables A0, A1, and A2. 13 DIGITAL SYSTEMS TCE1111 Example of a 5 to 32 Bit Decoder 14 DIGITAL SYSTEMS TCE1111 Logic symbol for a 4-line-to-16-line (1-of-16) decoder. 74HC154 15 DIGITAL SYSTEMS TCE1111 4-line-to-16 line Decoder constructed with two 3-line-to-8 line decoders (1)... 16 DIGITAL SYSTEMS TCE1111 4-line-to-16 line Decoder constructed with two 3-line-to-8 line decoders (2) When w=0, the top decoder is enabled and the other is disabled. The bottom decoder outputs are all 0’s , and the top eight outputs generate min-terms 0000 to 0111. When w=1, the enable conditions are reversed. The bottom decoder outputs generate min-terms 1000 to 1111, while the outputs of the top decoder are all 0’s. 17 DIGITAL SYSTEMS TCE1111 Application example A simplified computer I/O port system with a port address decoder with only four address lines shown. 18 DIGITAL SYSTEMS TCE1111 Decoders are used in many types of applications. One example is in computers for I/O selection as in previous slide Computer must communicate with a variety of external devices called peripherals by sending and/or receiving data through what is known as input/output (I/O) ports Each I/O port has a number, called an address, which uniquely identifies it. When the computer wants to communicate with a particular device, it issues the appropriate address code for the I/O port to which that particular device is connected. The binary port address is decoded and appropriate decoder output is activated to enable the I/O port Binary data are transferred within the computer on a data bus, which is a set of parallel lines 19 DIGITAL SYSTEMS TCE1111 BCD -to- Decimal decoders The BCD- to-decimal decoder converts each BCD code into one of Ten Positionable decimal digit indications. It is frequently referred as a 4-line -to- 10 line decoder The method of implementation is that only ten decoding gates are required because the BCD code represents only the ten decimal digits 0 through 9. Each of these decoding functions is implemented with NAND gates to provide active -LOW outputs. If an active HIGH output is required, AND gates are used for decoding 20 DIGITAL SYSTEMS TCE1111 Logic diagram of BCD - decimal decoder (Active LOW output) 21 DIGITAL SYSTEMS TCE1111 Output Waveform for BCD Decoder 22 DIGITAL SYSTEMS TCE1111 A Decoder Application - Counter -decoder combination used to provide timing and sequential operations (1)... 23 DIGITAL SYSTEMS TCE1111 A Decoder Application - Counter -decoder combination used to provide timing and sequential operations (1)... Decoders are used whenever an output or a group of outputs is to be activated only on the occurrence of specific combination of input levels. These input levels are often provided by the outputs of a counter or register. When the decoder inputs come from a counter that is being continually pulsed, the decoder outputs will be activated sequentially, and there can be used as timing or sequencing signals to turn device on or off at specific times 24 DIGITAL SYSTEMS TCE1111 BCD-7segment decoders/drivers Most digital equipment has some means for displaying information in a form that can be understood by the user. This information is often numerical data but also be alphanumeric. One of the simplest and most popular methods for displaying numerical digits uses a 7-segment configuration to form digital characters 0 to 9 and some times the hex characters A to F 25 DIGITAL SYSTEMS TCE1111 One common arrangements uses light-emitting diodes (LED's) for each segment. By controlling the current thru each LED, some segments will be light and others will be dark so that desired character pattern will be generated Figure shows the segment pattern that are used to display the various digits. For example, to display a “6” the segments a,c,d,e,f and g are made bright while segment b is dark 26 DIGITAL SYSTEMS TCE1111 7-segment decoder A BCD-7 segment decoder/driver is used to take four-bit BCD input and provide the outputs that will pass current through the appropriate segments to display the decimal digit. The logic for this decoder is more complicated than the logic of decoders of earlier case, because each output is activated for more than one combination of inputs. 27 DIGITAL SYSTEMS TCE1111 74LS47 ( BCD−to−Seven−Segment Decoder) 28 DIGITAL SYSTEMS TCE1111 29 DIGITAL SYSTEMS TCE1111 Lamp Test (LT) When LT = Low, BI/RBO = HIGH then all of the 7 segments in display are turned zero, LT is used to verify that no segments are burned out Zero Suppression (BI, RBI, RBO) Zero suppression is a feature used for multi digit displays to blank out unnecessary zeros. Example: In a 6-digit display the number 6.4 may be displayed as 006.400 if the zeros are not blanked out 30 DIGITAL SYSTEMS TCE1111 Leading Zero Suppression Blanking the zeros at the front of a numbers Trailing Zero Suppression Blanking the zeros at the back of the number Only nonessential zeros are blanked, the number 030.080 will be displayed as 30.08 (the essential zeros remain) 31 DIGITAL SYSTEMS TCE1111 7-segment display There are two types of 7−segment LED displays; A) common - anode B) common − cathode 32 DIGITAL SYSTEMS TCE1111 Common Anode In common−anode, the anode of all of the LEDs are tied together to positive of the power supply (Vcc) as shown 33 DIGITAL SYSTEMS TCE1111 Common Cathode In common−cathode, the cathode of all of the LEDs are tied together to ground as shown. GND 34 DIGITAL SYSTEMS TCE1111 Combinational Logic Circuit Implementation using a Decoder Any combinational logic circuit with n inputs and m outputs can be implemented with an n-to-2n-line decoder and m OR gates. Procedure: – Express the given Boolean function in sum of min-terms – Choose a decoder to generate all the min-terms of the input variables. – Select the inputs to each OR gate from the decoder outputs according to the list of min-term for each function. 35 DIGITAL SYSTEMS TCE1111 Combinational Logic Circuit Implementation using a Decoder - An example (1) From the truth table of the full adder, x y Z C S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 the functions can be expressed in sum of min-terms. S(x,y,z) = Σm(1,2,4,7) C(x,y,z) = Σm(3,5,6,7) where Σ indicates sum, m indicates min-term and the number in brackets indicate the decimal equivalent 36 DIGITAL SYSTEMS TCE1111 Combinational Logic Circuit Implementation using a Decoder - An example (2) Since there are three inputs and a total of eight min-terms, we need a 3-to-8 line decoder. The decoder generates the eight min-terms for x,y,z The OR gate for output S forms the logical sum of min-terms 1,2,4, and 7. The OR gates for output C forms the logical sum of min-terms 3,5,6, and 7 37 DIGITAL SYSTEMS TCE1111 Combinational Logic Circuit Implementation using a Decoder - example (3) Implementation of a Full Adder with a38 Decoder DIGITAL SYSTEMS TCE1111 Encoder An encoder is a combinational logic circuit that essentially performs a “reverse” of decoder functions. An encoder accepts an active level on one of its inputs, representing digit, such as a decimal or octal digits, and converts it to a coded output such as BCD or binary. Encoders can also be devised to encode various symbols and alphabetic characters. The process of converting from familiar symbols or numbers to a coded format is called encoding. 39 DIGITAL SYSTEMS TCE1111 Most decoders accept an input code and produce a HIGH ( or a LOW) at one and only one output line. In otherworlds , a decoder identifies, recognizes, or detects a particular code. The opposite of this decoding process is called encoding and is performed by a logic circuit called an encoder. An encoder has a number of input lines, only one of which input is activated at a given time and produces an N-bit output code,depending on which input is activated. 40 DIGITAL SYSTEMS TCE1111 General encoder diagram 41 DIGITAL SYSTEMS TCE1111 Logic circuit for octal-to binary encoder [8-line- 3-line ] 42 DIGITAL SYSTEMS TCE1111 Truth table for octal-to binary encoder [8-line- 3-line ] A low at any single input will produce the output binary code corresponding to that input. For instance , a low at A3’ will produce O2 =0, O1=1 and O0 =1, which is binary code for 3. Ao’ is not connected to the logic gates because the encoder outputs always be normally at 0000 when none of the inputs is LOW 43 DIGITAL SYSTEMS TCE1111 Design of 4-input Priority Encoder ( 4-line-to 2 line priority encoder) (1)... A priority encoder is an encoder that includes the priority function If two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. Truth Table of a 4-input Priority Encoder: Inputs Outputs D0 D1 D2 D3 x y V 0 0 0 0 X X 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1 44 DIGITAL SYSTEMS TCE1111 Design of 4-input Priority Encoder ( 4-line-to 2 line priority encoder) (2)... In addition to two outputs x, and y, the truth table has a third output designated by V, which is a valid bit indicator that is set 1 when one or more inputs are equal to 1. If all inputs are 0, there is no valid input and V is equal to 0. X’s in the output column indicate don’t care conditions, the X’s in the input columns are useful for representing a truth table in condensed form. The higher the subscript number, the higher the priority of the input. Input D3 has the highest priority, so regardless of the values of the other inputs, when this input is 1, the output for xy is 11 (binary 3) 45 DIGITAL SYSTEMS TCE1111 Design of 4-input Priority Encoder ( 4-line-to 2 line priority encoder) (3)... V=D0+D1+D2+D3 K-Maps for 4-input Priority Encoder 46 DIGITAL SYSTEMS TCE1111 Design of 4-input Priority Encoder ( 4-line-to 2 line priority encoder) (4) Logic Diagram for 4-input priority encoder 47 DIGITAL SYSTEMS TCE1111 Decimal-BCD priority encoder Encoder will produce a BCD output corresponding to the highest-order decimal digit input that is active and will ignore any other lower order active inputs. For instance if the input 6 and the 3 are active, the output will be 1001, which is the inverse value of BCD output 0110 (which represents decimal 6) 48 DIGITAL SYSTEMS TCE1111 74147 decimal-BCD priority encoder When A9’ is low, the output is 0110, which is inverse of 1001 ( eq to 9 in BCD) 49 DIGITAL SYSTEMS TCE1111 Decimal- BCD switch decoder The output of the decoder are inversed to produce the normal BCD value 50 DIGITAL SYSTEMS TCE1111 The Octal−to−Binary Priority Encoder-Example The 74LS148 is a priority encoder that has eight active LOW inputs and three active−LOW binary outputs To enable the device, the EI (enable input) must be LOW. It also has the EO (enable output) and GS (group signal output) for expansion purposes. 51 DIGITAL SYSTEMS TCE1111 The Octal−to−Binary Encoder 52 DIGITAL SYSTEMS TCE1111 The Octal−to−Binary Encoder Active−LOW enable input, a HIGH on the input forces all outputs to their inactive state (HIGH). Active−LOW enable output, the output pin goes LOW when all inputs are inactive (HIGH) and is LOW. Active−LOW group signal output, this output pin goes LOW whenever any of the inputs are active (LOW) and is LOW. 53 DIGITAL SYSTEMS TCE1111 The 16 −to−4 Encoder The 74LS148 can be expanded to a 16−line−to−4−line encoder by connecting the EO of the higher−order encoder to the EI of the lower−order encoder and negative−ORing the corresponding binary outputs as shown 54 DIGITAL SYSTEMS TCE1111 The 16 −to−4 Encoder 55 DIGITAL SYSTEMS TCE1111 Application example A simplified keyboard encoder. 56 DIGITAL SYSTEMS TCE1111 When one of the keys is pressed, the decimal digit is encoded to the corresponding BCD code The keys are represented by 10 push-button switches, each with a pull-up resistor to V+. The pull-up resistor ensures that the line is HIGH when a key is not depressed. When a key is depressed, the line is connected to ground, and a LOW is applied to the corresponding encoder input. The zero key is not connected because the BCD output represents zero when none of the other keys is depressed The BCD complement output of the encoder goes into a storage device, and each successive BCD code is stored until the entire number has been entered 57 DIGITAL SYSTEMS TCE1111 Exercise Sketch the output waveforms of the 74LS148 encoder based on the given waveforms. Assume that 58  H ARDWARE D ESCRIPTION LANGUAGE (HDL)  OUTLINE A Brief History of HDL Structure of HDL Module Operators Data types Types of Descriptions simulation and synthesis VHDL Design units Brief comparison of VHDL and Verilog  WHY HDL HDL is a CAD tool for modern design and synthesis of Digital Systems. The recent steady advances in semiconductor technology continue to increase the power and complexity of Digital Systems. Discrete IC implementation is difficult hence high density PLDs and CAD tools are required. HDL is an integral part of such tools HDL offers the designer a very efficient tool for implementing and synthesizing designs on chips. The designer uses HDL to describe the system in a computer language that is similar to several common languages. Two widely used HDL are VHDL and Verilog.  A BRIEF HISTORY OF VHDL VHDL stands for Very High Speed Integrated circuit(VHSIC) Hardware Description Language 1981Initiated by US address hardware life-cycle crisis(gate level) 1983-85Development of baseline language by Inter metrics, IBM and TI 1986All rights transferred to IEEE 1987Publication of IEEE Standard  A BRIEF HISTORY OF VHDL ASICs 1994Revised standard (named VHDL 1076-1993) 2000Revised standard (named VHDL 1076 2000, Edition) 2002Revised standard (named VHDL 1076-2002) 2007VHDL Procedural Language Application Interface standard (VHDL 1076c-2007) 2009Revised Standard (named VHDL 1076-2008)  STRUCTURE OF THE HDL MODULE Structure of the VHDL can be divided into two major parts and they are: Entity, Architecture Entity is a part of the VHDL where we declare all the inputs and outputs of the program. We give some identifier names for the input and output in this part. VHDL is case insensitive module, you can use both upper case and lower case in this module. We have some rules to write entity name  STRUCTURE OF THE HDL MODULE We have some rules to write entity name The first letter of the entity should be alphabet. Special characters should not be allowed except underscore(_). Two underscore(_) continuously not allowed. The last cannot end with special character. Example: Entity and_gate is port(A : in bit; B : in bit; Y : out bit); end and_gate;  STRUCTURE OF THE HDL MODULE Architecture is part where we declare the relation ship between the inputs and output. We can write more than one architecture for the same entity. The architecture is a pre-defined word. For example: architecture gate of and_gate is Y sum); A1: and2 port map(I1=> a, I2=> b, O1 =>cout); End exple;  DATA-FLOW DESCRIPTIONS Example: Entity halfadder_is Port(a,b: in bit; s,c:out bit); End halfadder; Architecture ha_dtfl of halfadder is Begin S