Logic Circuits for Digital Systems PDF

**Logic Circuits for Digital Systems** Logic circuits are the fundamental building blocks of digital systems. They are used to process, control, and manage binary data (0s and 1s) in a variety of digital devices, including computers, communication systems, and embedded systems. **Types of Logic Ci...

**Logic Circuits for Digital Systems** Logic circuits are the fundamental building blocks of digital systems. They are used to process, control, and manage binary data (0s and 1s) in a variety of digital devices, including computers, communication systems, and embedded systems. **Types of Logic Circuits** **1. Combinational Logic Circuits:** The output depends only on the current inputs, not on past inputs. **2. Sequential Logic Circuits:** The output depends on both the current inputs and the past state (uses memory elements). **Representation of Logic Circuits** - **Truth Tables** - **Boolean Expressions** - **Logic Diagrams (**Graphical representation of a circuit using symbols for gates and connections.) **Combinational Logic circuits** A combinational circuit consists of an interconnection of logic gates. The combinational logic circuits are the circuits that contain different types of logic gates. Simply, a circuit in which different types of logic gates are combined is known as a **combinational logic circuit**. The output of the combinational circuit is determined from the present combination of inputs, regardless of the previous input. The input variables, logic gates, and output variables are the basic components of the combinational logic circuit. There are different types of combinational logic circuits, such as Adder, Subtractor, Decoder, Encoder, Multiplexer, and De-multiplexer. *There are the following characteristics of the combinational logic circuit:* - At any instant of time, the output of the combinational circuits depends only on the present input terminals. - The combinational circuit doesn\'t have any backup or previous memory. The present state of the circuit is not affected by the previous state of the input. - The n number of inputs and m number of outputs are possible in combinational logic circuits. The \'n\' input variable comes from the external source while the \'m\' output variable goes to the external destination. In many applications, the source or destinations are storage registers. **Half Adder** The half adder is a basic building block having two inputs and two outputs. The adder is used to perform [OR](https://www.javatpoint.com/or-gate-in-digital-electronics) operation of two single bit binary numbers. The **carry** and **sum** are two output states of the half adder. **Full Adder** The half adder is used to add only two numbers. To overcome this problem, the full adder was developed. The full adder is used to add three 1-bit binary numbers A, B, and carry C. The full adder has three input states and two output states i.e., sum and carry. **Half Subtractors** The half subtractor is also a building block of subtracting two binary numbers. It has two inputs and two outputs. This circuit is used to subtract two single bit binary numbers A and B. The **\'diff**\' and **\'borrow\'** are the two output state of the half adder. **Full Subtractors** The Half Subtractor is used to subtract only two numbers. To overcome this problem, full subtractor was designed. The full subtractor is used to subtract three 1-bit numbers A, B, and C, which are **minuend, subtrahend**, and **borrow,** respectively. The full subtractor has three input states and two output states i.e., diff and borrow. **Multiplexers** The multiplexer is a combinational circuit that has n-data inputs and a single output. It is also known as the **data selector** which selects one input from the inputs and routes it to the output. With the help of the selected inputs, one input line from the n-input lines is selected. The enable input is denoted by E, which is used in cascade. **De-multiplexers** A De-multiplexer performs the reverse operation of a multiplexer. The de-multiplexer has only one input, which is distributed over several outputs. One output line is selected at a time by selecting lines. The input is transmitted to the selected output line. **Encoder** An **encoder** is a device, circuit, or algorithm that converts information from one format or representation into another, typically to enable efficient processing, transmission, or storage. An encoder having n number of inputs and m number of outputs is used to produce m-bit binary code which is related to the digital input number. The encoder takes the digital word and converts it into another digital word. **Decoder** A **decoder** is a device, circuit, or algorithm that reverses the encoding process, converting encoded data back into its original format or a more useful form. A decoder is a combinational circuit having n inputs and to a maximum of m = 2^n^ outputs. The decoder is the same as the de-multiplexer. The only difference between de-multiplexer and decoder is that in the decoder, there is no data input. **Half Adder** The Half-Adder is a basic building block of adding two numbers as two inputs and produce out two outputs. The adder is used to perform OR operation of two single bit binary numbers. The **augent** and **addent** bits are two input states, and **\'carry**\' and **\'sum** \'are two output states of the half adder.  In S The SOP (Sum of Product) form of the sum and carry are as follows: ***Construction of Half Adder Circuit:*** In the block diagram, we have seen that it contains two inputs and two outputs. The **augent** and **addent** bits are the input states, and **carry** and **sum** are the output states of the half adder. The half adder is designed with the help of the following two logic gates: 1. 2-input AND Gate. 2. 2-input Exclusive-OR Gate or Ex-OR Gate 1. **2-input Exclusive-OR Gate or Ex-OR Gate** The **Sum** bit is generated with the help of the **Exclusive-OR** or **Ex-OR** Gate. The truth table of the EX-OR gate is as follows: From the above table, it is clear that the [XOR gate](https://www.javatpoint.com/xor-gate-in-digital-electronics) gives the result 1 when both of the inputs are different. When both of the inputs are the same, the XOR gives the result 0. 2. **2-input AND Gate:** The XOR gate is unable to generate the carry bit. For this purpose, we use another gate called [AND Gate](https://www.javatpoint.com/and-gate-in-digital-electronics). The AND gate gives the correct result of the carry. The above is the symbol of the **AND** gate. In the above diagram, \'A\' and \'B\' are the inputs, and \'OUT\' is the final outcome after performing AND operation of both numbers. There is the following truth table of AND Gate: From the above table, it is clear that the AND gate gives the result 1 when both of the inputs are 1. When both of the inputs are different and 0, the AND gates gives the result 0. **Half-Adder logical circuit:** So, the Half Adder is designed by combining the \'XOR\' and \'AND\' gates and provide the sum and carry.  There is the following **Boolean expression** of **Half Adder circuit**: **Full Adder** A full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of three inputs and two outputs. The half adder is used to add only two numbers. To overcome this problem, the full adder was developed. The full adder is used to add three 1-bit binary numbers A, B, and carry C. The full adder has three input states and two output states i.e., sum and carry. In the above table, 1. \'A\' and\' B\' are the input variables. These variables represent the two significant bits which are going to be added 2. \'C~in~\' is the third input which represents the carry. From the previous lower significant position, the carry bit is fetched. 3. The \'Sum\' and \'Carry\' are the output variables that define the output values. 4. The eight rows under the input variable designate all possible combinations of 0 and 1 that can occur in these variables. Note: We can simplify each of the output \'Boolean function\' with the help of the unique map method. The SOP form can be obtained with the help of K-map as: ***Construction of Half Adder Circuit:*** **The above block diagram describes the construction of the Full adder circuit**. In the above circuit, there are two half adder circuits that are combined using the OR gate. The first half adder has two single-bit binary inputs A and B. As we know that, the half adder produces two outputs, i.e., Sum and Carry. The \'Sum\' output of the first adder will be the first input of the second half adder, and the \'Carry\' output of the first adder will be the second input of the second half adder. The second half adder will again provide \'Sum\' and \'Carry\'. The final outcome of the Full adder circuit is the \'Sum\' bit. In order to find the final output of the \'Carry\', we provide the \'Carry\' output of the first and the second adder into the OR gate. The outcome of the OR gate will be the final carry out of the full adder circuit. The MSB is represented by the final \'Carry\' bit. The full adder logic circuit can be constructed using the **\'AND\'** and **the \'[XOR\' gate](https://circuitdigest.com/electronic-circuits/and-gate-circuit-working)** with an [**OR gate**](https://circuitdigest.com/electronic-circuits/or-gate-circuit). **OR** The actual logic circuit of the full adder is shown in the above diagram. The full adder circuit construction can also be represented in a Boolean expression. Sum: - Perform the XOR operation of input A and B. - Perform the XOR operation of the outcome with carry. So, the sum is (A XOR B) XOR C~in~ which is also represented as: Carry: 1. Perform the \'AND\' operation of input A and B. 2. Perform the \'XOR\' operation of input A and B. 3. Perform the \'OR\' operations of both the outputs that come from the previous two steps. So the \'Carry\' can be represented as: **Binary Adder** A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of the next full adder in the chain. Addition of n-bit numbers requires: - **a chain of n full adders or** - **a chain of one half adder and n- 1 full adders.** An n-bit adder requires n full adders, with each output carry connected to the input carry of the next higher order full adder. - In the former case, the input carry to the least significant position is fixed at 0. - Figure shows the connection of four full--adder (FA) circuits to provide a four-bit binary ripple carry adder. - The augend bits of A and the addend bits of B are designated by subscript numbers from right to left, with subscript 0 denoting the least significant bit. - The carries are connected in a chain through the full adders. The input carry to the adder is C~0~, and it ripples through the full adders to the output carry C~4~. - The S outputs generate the required sum bits. To demonstrate with a specific example, consider the two binary numbers A = 1011 and B = 0011. Their sum S = 1110 is formed with the four-bit adder as follows: **Half Subtractor** The half subtractor is also a building block for subtracting two binary numbers. It has two inputs and two outputs. This circuit is used to subtract two single bit binary numbers A and B. The **\'diff**\' and **\'borrow\'** are two output states of the half subtractor. The SOP form of the **Diff** and **Borrow** is as follows: In the above table, - \'A\' and \'B\' are the input variables whose values are going to be subtracted. - The \'Diff\' and \'Borrow\' are the variables whose values define the subtraction result, i.e., difference and borrow. - The first two rows and the last row, the difference is 1, but the \'Borrow\' variable is 0. - The third row is different from the remaining one. When we subtract the bit 1 from the bit 0, the borrow bit is produced. ***Construction of Half Subtractor Circuit*** In the block diagram, we have seen that it contains two inputs and two outputs. The **carry** and **sum** are the output states of the half subtractor. The half subtractor is designed with the help of the following logic gates: 1. 2-input AND gate. 2. 2-input Exclusive-OR Gate or Ex-OR Gate 3. NOT or inverter Gate 1\. 2-input Exclusive-OR Gate or Ex-OR Gate The **Diff** bit is generated with the help of the **Exclusive-OR** or **Ex-OR** gate. The above is the symbol of the **EX-OR** gate. In the above diagram, \'A\' and \'B\' are the inputs, and **\'Diff\'** is the final outcome after performing the XOR operation of both numbers. **2. 2-input AND gate:** The XOR gate is unable to generate the carry bit. For this purpose, we use another gate called [AND gate](https://www.javatpoint.com/and-gate-in-digital-electronics). The AND gate is not enough to give the correct result of **\'Borrow\'**. We will use the [NOT gate](https://www.javatpoint.com/not-gate-in-digital-electronics) with the \'AND\' gate to get the correct result. There is the following truth table of AND gate: The above is the symbol of the **AND** gate. In the above diagram, \'A\' and \'B\' are the inputs, and \'OUT\' is the final outcome after performing AND operation of both numbers. **3. NOT or Inverter Gate:** The NOT gate is used to get the inverse output. We can combine the \'AND\' and \'NOT\' gates in order to get the combinational gate \'NAND\'. By inverting the input \'A\' using \'NOT\' gate and then use the output of the \'NOT\' gate as the input of the \'AND\' gate, we can get the \'Borrow\' bit.  **Half-Subtractor logical circuit** So, the Half Subtractor is designed by combining the \'XOR\', \'AND\', and \'NOT\' gates and provide the Diff and Borrow. The **Boolean expression** of the **Half Adder circuit** is given below: