Lecture 1_بناء حاسب PDF

William Stallings Computer Organization and Architecture Chapter 3 Top Level View of Computer Function and Interconnection  Top Level View of Computer Function and Interconnection 3.1 Computer Components 3.2 Computer Function Instruction Fetch and Execute Interrupts...

William Stallings Computer Organization and Architecture Chapter 3 Top Level View of Computer Function and Interconnection  Top Level View of Computer Function and Interconnection 3.1 Computer Components 3.2 Computer Function Instruction Fetch and Execute Interrupts I/O Function 3.3 Interconnection Structures 3.4 Bus Interconnection Bus Structure Multiple-Bus Hierarchies Elements of Bus Design 3.5 PCI Bus Structure PCI Commands Data Transfers Arbitration Program Concept Hardwired System Assuming that we have a small set of basic logic components that can be combined in various ways to store binary data and perform arithmetic and logical operations on that data If there is a particular computation to be performed, a configuration of logic components designed specifically for that computation could be constructed This technique is called hardwired system It is a customized hardware that accepts data and produces results Program Concept Hardwired program A B C A B C Adder Compute A+B-C Subtractor Special purpose hardware Program Concept Software System ❑ Suppose we construct a general-purpose configuration of arithmetic and logic functions ❑ This set of hardware will perform various functions on data depending on control signals applied to hardware ❑ With general-purpose hardware, the system accepts data and control signals and produces results ❑ Thus, instead of rewiring the hardware for each new function, the designer merely needs to supply a new set of control signals ❑ The new set of control signals is defined by a sequence of commands usually called “Program” Program Concept Software System Control Unit Constitute CPU But Several other components are needed to yield a functioning computer ❑ Programming is now much easier. ❑ Instead of rewiring the hardware for each new function, all we need to do is to provide a new sequence of codes. ❑ Each code is, in effect, an instruction, and ❑ Part of the hardware interprets each instruction and generates control signals Program Concept ❑ Hardwired systems are inflexible ❑ General purpose hardware can do different tasks, given correct control signals ❑ Instead of re-wiring, supply a new set of control signals What is a program? ❑ A sequence of steps ❑ For each step, an arithmetic or logical operation is done ❑ For each operation, a different set of control signals is needed Components ❑ The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit ❑ Data and instructions need to get into the system and results out ✓ Input/output ❑ Temporary storage of code and results is needed ✓ Main memory Memory Location 123 0 Word length = n 710 1 Memory Controller Data Bus n-bits 200 2 -50 3 Memory size = 2m 4 123 Address Bus m-bits 710 5 Read 200 6 Control Bus Write -50 7 Components ❑ The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit ❑ Data and instructions need to get into the system and results out ✓ Input/output ❑ Temporary storage of code and results is needed ✓ Main memory Memory Location 123 0 710 1 Memory Controller Data Bus 200 2 Read Location -50 3 3 123 4 Address Bus 3 710 5 Read 200 6 Write -50 7 Components ❑ The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit ❑ Data and instructions need to get into the system and results out ✓ Input/output ❑ Temporary storage of code and results is needed ✓ Main memory Memory Location 123 0 710 1 Memory Controller Data Bus 200 2 Read Location -50 3 6 123 4 Address Bus 6 710 5 Read 200 6 Write -50 7 Components ❑ The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit ❑ Data and instructions need to get into the system and results out ✓ Input/output ❑ Temporary storage of code and results is needed ✓ Main memory Memory Location 123 0 710 1 Memory Controller Data Bus 35 200 2 Write 35 to -50 3 Location 5 123 4 Address Bus 5 710 35 5 Read 200 6 Write -50 7 Computer Components: Top Level View CPU Main Memory PC MAR System Instruction 0 MBR BUS Instruction 1 IR Instruction 2 I/O AR. Execution. Unit I/O BR. Data I/O Module Data Buffers Data n-2 n-1 Date: / Computer Components: Top Level View ❑ Memory Address Register (MAR), specifies the address in memory for the next read or write ❑ Memory Buffer Register (MBR), contains the data to be written into memory or receives data read from memory ❑ Similarly, an I/O address register (I/O AR) specifies a particular I/O device ❑ Memory module consists of a set of locations, defined by sequentially numbered addresses ❑ Each location contains a binary number that can be interpreted as either an instruction or data ❑ I/O buffer register (I/O BR) is used for the exchange of data between an I/O module and the CPU ❑ An I/O module transfers data from external devices to CPU and memory, and vice versa ❑ I/O module contains internal buffers for temporarily holding these data until they can be sent on Instruction Cycle ❑ Two steps: Fetch Execute Fetch Next Execute Start Halt Instruction Instruction Fetch Cycle ❑Program Counter (PC) holds address of next instruction to fetch ❑Processor fetches instruction from memory location pointed to by PC ❑Increment PC Unless told otherwise ❑Instruction loaded into Instruction Register (IR) ❑Processor interprets instruction and performs required actions Execute Cycle ❑Processor-memory Data transfer between CPU and main memory ❑Processor I/O Data transfer between CPU and I/O module ❑Data processing Some arithmetic or logical operation on data ❑Control Altering the execution sequence e.g. jump ❑Combination of above Example of Program Execution Hypothetical machine ❑ The processor contains a single data register, called an accumulator (AC) ❑ Both instructions and data are 16 bits long ❑ Thus, it is convenient to organize memory using 16-bit words ❑ The instruction format provides 4 bits for the opcode, so that there can be as many as 24 = 16 different opcodes and ❑ up to 212 = 4096 (4K) words of memory can be addressed 0001→ load AC from memory LDA {address} 0010→ store AC to memory STA {address} 0101→ add to AC from memory ADA {address} Instruction 15 12 11 0 0010 100101000000 Op-Code Address STA {940}Hex 2 9 4 0 Example of Program Execution Fetch Memory Program CPU Registers 300 1940 LDA {940} 300 PC 301 5941 ADA {941} AC 302 2941 STA {941} IR 940 0003 941 0002 0001→ load AC from memory 0010→ store AC to memory 0101→ add to AC from memory Example of Program Execution Execute Op-Address Memory Program CPU Registers 1-940 300 1940 LDA {940} 301 300 PC Load Acc from 301 5941 ADA {941} AC address 940 302 2941 STA {941} 1940 IR 940 0003 941 0002 0001→ load AC from memory 0010→ store AC to memory 0101→ add to AC from memory Example of Program Execution Fetch Memory Program CPU Registers 300 1940 LDA {940} 301 PC 301 5941 ADA {941} 0003 AC 302 2941 STA {941} 1940 5941 IR 940 0003 941 0002 0001→ load AC from memory 0010→ store AC to memory 0101→ add to AC from memory Example of Program Execution Execute Op-Address Memory Program CPU Registers 5-941 300 1940 LDA {940} 302 301 PC Add Acc with 301 5941 ADA {941} 0003 0005 AC address 941 302 2941 STA {941} 5941 IR 940 0003 + = 0005 941 0002 0001→ load AC from memory 0010→ store AC to memory 0101→ add to AC from memory Example of Program Execution Fetch Memory Program CPU Registers 300 1940 LDA {940} 302 301 PC 301 5941 ADA {941} 0005 AC 302 2941 STA {941} 5941 2941 IR 940 0003 941 0002 0001→ load AC from memory 0010→ store AC to memory 0101→ add to AC from memory Example of Program Execution Execute Op-Address Memory Program CPU Registers 2-941 300 1940 LDA {940} 302 301 303 PC Store Acc to 301 5941 ADA {941} 0005 AC address 941 302 2941 STA {941} 2941 IR 940 0003 941 0002 0005 0001→ load AC from memory 0010→ store AC to memory 0101→ add to AC from memory Example of Program Execution Example of Program Execution ❑ In this example, three instruction cyclesare needed to add the contents of location 940 to the contents of 941 ❑ With a more complex set of instructions, fewer cycles would be needed ❑ Some older processors, include instructions that contain more than one memory address In order that the contents of A ❑ The execution cycle for a particular instruction on such are not lost, the processor must processors could involve more than one reference to memory have at least two registers for ❑ For example, the PDP-11 storing processor includes memory values,an instruction, rather expressed symbolically asthan ADD a B,A single accumulator. 1. Fetch the ADD instruction. 2. Read the contents of memory location A into the processor. 3. Read the contents of memory location B into the processor. 4. Add the two values. 5. Write the result from the processor to memory location A Instruction Cycle State Diagram ❑ In general, the execution cycle for a particular instruction may involve more than one reference to memory or I/O ❑ With these additional considerations in mind, a more detailed instruction cycle can be discussed Instruction Operand Operand fetch fetch store Multiple Multiple operands Results Instruction Operand Operand Instruction Data Address Address address decoding operation calculation calculation calculation Instruction Ends Fetch Return for next instruction Vector data Instruction Cycle State Diagram ❑ In general, the execution cycle for a particular exchangeinstruction between may involve more than one reference to memory or I/O processor and either ❑ With these additional considerations inmemory mind, aormore an I/O detailed instruction cycle can be discussed module Instruction Operand Operand fetch fetch store internal processor Multiple Multiple operations operands Results Instruction Operand Operand Instruction Data Address Address address decoding operation calculation calculation calculation Instruction Ends Fetch Return for next instruction Vector data Instruction Cycle State Diagram The states of instruction cycle can be described as follows ❑ Instruction address calculation (iac): Determine the address of the next instruction to be executed ❑ Instruction fetch (if): Read instruction from its memory location into processor. ❑ Instruction operation decoding (iod): determine type of operation to be performed and operand(s) to be used. ❑ Operand address calculation (oac): determine the address of the operand in memory or available via I/O ❑ Operand fetch (of): Fetch the operand from memory or read it in from I/O. ❑ Data operation (do): Perform the operation indicated in the instruction. ❑ Operand store (os): Write the result into memory or out to I/O.