Interrupts Lecture Notes

Interrupts Polling Vs Interrupts o We have seen processors are interfaced with a variety of peripherals o Sometimes peripherals much much slower compared to the processor (executing instructions) o This is especially true if the peripherals have mechanical parts o Sometimes...

Interrupts Polling Vs Interrupts o We have seen processors are interfaced with a variety of peripherals o Sometimes peripherals much much slower compared to the processor (executing instructions) o This is especially true if the peripherals have mechanical parts o Sometimes peripherals need external data (sensors, network etc.) o That also slows them down 2 Polling Vs Interrupts o Consider the example with a printer o Processor sends data to the printer then it needs to figure out what happened o Printing may be successful; some error due to page jamming, or no paper left o The figure out the status of the printer, processor needs to continuously read some control signal (such as the ACK signal) or some register inside the printer control chip o This continuous reading to check the status is called polling o As you can see polling is highly inefficient since the processor is stuck in reading status and not doing any useful job 3 Polling Vs Interrupts o Instead of processor continuously checking the peripheral, what if the peripheral somehow informs the processor it needs attention? o For example in case of printer, processor sends data to printer and continue with other jobs o The printer will request for processor attention in case it successfully completes the job or any error occurs o This mechanism of a peripheral requesting for processor attention is interrupt o Interrupts make systems very efficient since they can bring concurrently into the system o Processor is not stuck with one peripheral and multiple peripherals can execute in parallel 4 Polling Vs Interrupts o The interrupt mechanism may be implemented using a physical signal from peripheral to the processor (legacy interrupts) or a special data pattern sent to the processor (such as the MSI in PCIe) o Modern systems use a mix of both (such as in USB), where a USB host keeps polling USB devices and the host itself interrupts the processor (chipset) o To distinguish between interrupts from different peripherals (or even multiple interrupts from each peripheral), each interrupt is associated with a unique number called the interrupt request number (IRQ number or type in 8086) o Upon receiving an interrupt processor executes a special function/subroutine called interrupt service routine (ISR) 5 8086 Sources of Interrupts o x86 processors may receive interrupts externally or internally (software generated/exceptions) o External interrupts may arrive through 2 pins, INTR (Interrupt) and NMI (Non- maskable Interrupt) o Software interrupt can be generated using INT instruction o Error conditions (generally referred as exceptions) such as divide by 0 or overflow will also generate interrupts 6 What happens when interrupt occurs o 8086 checks for any pending interrupt at the end of each instruction (not machine) cycle o upon detecting a pending interrupt o decrements stack pointer by 2 and pushes the flag register on the stack o disables the 8086 INTR Interrupt input by clearing the interrupt flag (IF) In the flag register and resets TRAP flag o decrements the stack pointer by 2 and pushes the current code segment register contents on the stack o decrements the stack pointer by 2 and pushes the current instruction pointer (effectively address of next instruction) 7 o does a far jump to the start of the ISR What happens when ISR is completed o There should be (at least one) IRET instruction in the ISR for returning o Once IRET is encountered o IP is popped from stack o Stack pointer is incremented by 2 and CS is popped o Flag register is popped o Continue with execution of the next instruction 8 Interrupt vectors and Interrupt Vector Table (IVT) o Starting address of an ISR is often called the interrupt vector o Unlike regular procedures, you won’t see any explicit call instruction for ISR o They are implicitly called when an interrupt occurs o Interrupt vectors are stored in a table called interrupt vector table o For 8086, 256 IRQs are supported, hence there could be up to 256 ISRs o Each interrupt vector require 4 bytes of storage (2 bytes of CS and 2 for IP) o Thus for 8086, total IVT size is 1 KB (4B*256) o For 8086 IVT is stored at a predefined location starting at 0000:0000H up to 0000:03FFH 9  Interrupt vectors and Interrupt Vector Table (IVT) o Intel has reserved certain IRQs (out of 256) for specific purposes Reserved 3FFH Type-255 Vector 016H Type-5 Vector 3FCH User defined 014H (RESERVED).. 012H Type-4 Vector.. User Defined Dedicated Interrupt Vectors 010H Overflow.. 00EH Type-3 Vector.. 00CH INT 3 Instruction.. 00AH Type-2 Vector.. 008H NMI.. 006H Type-1 Vector 082H Type-32 Vector 004H Single Step 080H User defined Reserved 002H Type-0 Vector 07FH Type-31 Vector 10 000H Divide by 0 Error 07DH (RESERVED) What happens when interrupt occurs o …………………………………….. CS Base Address o ……………………………………. IP Offset o decrements the stack pointer by 2 One IVT Entry (One interrupt vector) and pushes the current code segment register contents on the Using IRQ number, stack determine the IVT offset o decrements the stack pointer by 2 (IRQ*4) and pushes the current instruction From IVT load IP and CS pointer (effectively address of values next instruction) o does a far jump to the start of the ISR Start ISR 11 Type-0 Interrupt (IRQ-0 Interrupt) oAutomatically raised with division by zero exception happens Eg: xor bl,bl div bl oThe ISR IP offset should be at address 0x00000 and CS at 0x00002 oIf ISR is not explicitly written or the IVT is not properly initialized, system behaviour will be undefined oOnce this exception occurs, processor will blindly start executing from address specified in IVT 12 Type-0 Interrupt (IRQ-0 Interrupt) o Assuming the int 21H subroutines are available, write an ISR for type-0 interrupt, which displays the message “Error divide by zero”.model tiny.data errorMsg db 'Error divide by zero$'.code mov ax, 0000 mov es, ax mov word ptr es:0002, seg isr mov word ptr es:0000, offset isr mov bl,0 div bl hlt isr: lea dx,errorMsg mov ah,09h int 21h iret 13 (Don’t try this code with MASM) Type-1 Interrupt (IRQ-1 Interrupt) oAlso called the trap interrupt oMostly used for debugging (You were using this interrupt while using trace option in debugX) oThis interrupt is raised at the end of an instruction if the TRAP flag bit is set oOnce this interrupt occurs, after pushing flag, and CS and IP of next instruction to stack processor fetches ISR address from 0x00004 (IP) and 0x00006(CS) 14 Type-1 Interrupt (IRQ-1 Interrupt) o8086 has no single instruction to set of clear TRAP flag bit oIt is done with the help of stack memory PUSHF ;Push flags on stack MOV BP,SP ;Copy SP to BE' for use as index OR WORD PTR [BP+0],0100H ; Set TF bit POPF ;Restore flag register oPerforming AND operation with 0xFEFF will clear the trap flag 15 Type-1 Interrupt (IRQ-1 Interrupt) o With the help of trap interrupt, develop a debugger such that it displays the values of AX, BX, CX and DX registers after executing each instruction.model tiny.186.data.code mov AX, 0000 mov ES, AX mov word ptr ES:0006, seg isr mov word ptr ES:0004, offset isr pushf ;Push flags on stack mov BP,SP ;Copy SP to BE' for use as index or WORD PTR [BP+0],0100H ; Set TF bit 16 popf ;Restore flag register Type-1 Interrupt (IRQ-1 Interrupt) mov ax,10 mov bx,20.exit isr: push dx push cx push bx call showNum pop ax ;show bx call showNum pop ax ;show cx call showNum pop ax ;show dx 17 iret Type-1 Interrupt (IRQ-1 Interrupt) o8086 has no single instruction to set of clear TRAP flag bit oIt is done with the help of stack memory PUSHF ;Push flags on stack MOV BP,SP ;Copy SP to BE' for use as index OR WORD PTR [BP+0],0100H ; Set TF bit POPF ;Restore flag register oPerforming AND operation with 0xFEFF will clear the trap flag 18 Type- 2 Interrupt (IRQ-2 Interrupt) oTriggered by a low-to high transition (positive edge triggered) on the NMI pin oType 2 interrupt response cannot be disabled (masked) by any instruction oSo very system critical signal will be connected to NMI oAnother scenario is power good signal can be connected here so that when power fails, the system status (all registers and entire RAM) can be backed-up to a non-volatile memory oSystem may be powered with a super capacitor which gives just enough energy backup for this purpose 19 Type- 3 Interrupt (IRQ-3 Interrupt) oProduced by execution of INT 3 instruction oMain use of type 3 interrupt is to Implement a breakpoint oThey are very useful during debug oINT 3 is a single byte instruction (CCH) oWhen you ask the program to run till a certain address (such as using the go command in debugx), the instruction at the address is temporarily replaced with INT 3 oSo, the processor executes instructions till the breakpoint and calls the ISR for INT 3 oWhat actions are taken then depends on the ISR (May be you print all register contents) 20 Type- 4 Interrupt (IRQ-4 Interrupt) oThis is overflow interrupt oOverflow can happen when you perform arithmetic operation oLike we discussed before, in addition/subtraction overflow has significance only if the operands are unsigned oFor ADD, SUB there are no special indication whether operands are signed or unsigned oEg: MOV AL, 108 ADD AL, 81 oThe result in AL will be 189, there is no carry 21 Type- 4 Interrupt (IRQ-4 Interrupt) oBut overflow flag will be set in this case, because the binary for 189 is 10111101, which indicates the number is –ve in signed representation (-67) oFor the operands were positive 108 (01101100) and 81 (01010001) oThus, whether we care about overflow or not depends upon whether I was trying to do signed addition or not oProcessor does not care about it oBecause of this an overflow does not automatically trigger an interrupt oIf we care about overflow, we may use JO or JNO instructions 22 Type- 4 Interrupt (IRQ-4 Interrupt) oOr use a INTO instruction (interrupt on overflow) after the arithmetic operation oIf there is no overflow, INTO instruction acts like a NOP (processor does nothing) oBut if there is an overflow, it will go the interrupt service routing corresponding to INTO, whose address is stored in the IVT (CS value at 00012H and IP value at 00010H). 23 Software Interrupts o Software interrupts can be raised with the help of INT instruction o The IRQ number (type) is followed after INT o Eg: INT 21H o IRQ can be from 0 to 255 o Similar to previously discussed interrupts, the starting address of ISR is taken from the IVT o Using INT instruction, it will be possible to raise even the predefined instruction o For example, if you have INT 0 instruction anywhere in your program, when the processor executes the instruction is calls the same ISR defined for division by 0 error although there is no actual 24 division by 0 error INTR Interrupts (Hardware interrupts) oHardware peripherals can interrupt 8086 by sending a high signal on the INTR pin oINTR is a level triggered interrupt oUnlike NMI, INTR can be masked (disabled) oProcessor responds to an INTR signal only if the IF (Interrupt Flag) bit in the flag register is set o STI  Set Interrupt (Instruction to set the flag bit) o CLI  Clear interrupt (Instruction to clear the flag bit) o When 8086 is reset, IF flag by default set to 0 o This is done so that everything (peripherals, IVT etc.) are initialized before interrupt is enabled 25 INTR Interrupts (Hardware interrupts) oWe have seen that when an isr is called, IF flag is automatically cleared oThis is to prevent interrupt nesting (switching to another ISR from one ISR) oBut if your software can handle, you can reenable IF bit within the ISR oSince flag register is pushed to the stack before calling ISR and since restored after IRET is executed, IF bit will be automatically restored o In response to INTR, 8086 executes 2 interrupt acknowledge machine cycles by disserting INTA’ signal 26 INTR Interrupts (Hardware interrupts) oDuring the second cycle, when INTA’ is de-asserted, the interrupting peripheral should place the IRQ number (Interrupt type number) on the lower byte of data bus oUsing this number, 8086 fetches the starting address of the ISR from IVT and enters the ISR oHere also IRQ number can be anything from 0-255 oThat means a peripheral may choose to place 0 as the IRQ number and in response to that 8086 will execute the ISR corresponding to divide by 0 error. 27 Interrupt Acknowledge Cycle 28 Interrupt Priority oWhat happens more than one interrupt happens simultaneously (Eg: NMI and INTR) oThe interrupt with higher priority gets serviced first oInternal (INT n, INTO, Divide error etc.) are check before checking external interrupts (NMI, INTR) Interrupt Priority (Descending order) Divide error, INT n, INTO Highest NMI INTR Single Step (TRAP) Lowest oNB: Intel does not explicitly specifies priority levels except between NMI and INTR 29 Interrupt cases Case 1 Two software interrupts cannot happen simultaneously (Two instructions cannot execute simultaneously) It is possible to have a software interrupt with in the ISR of another software interrupt Thus, software interrupts are processed in the order the INT instructions are executed Case 2 Since IF flag is cleared at the beginning of ISR, INTR interrupt will not be detected while running any ISR Thus, interrupt nesting does not happen due to INTR unless you explicitly enable IF flag with in an ISR 30 Interrupt cases Case 3 If an NMI occurs when the processor is already in an ISR, the NMI will be serviced first It is applicable even when the system is executing the ISR for an NMI This may cause interrupt nesting and should consider during system design/software development It is possible to have software interrupts within NMI and they will be processed in the order the INT instruction is executed 31 Interrupt cases Case 4 If INTR and NMI (both external interrupts) occurs at exact same moment, NMI will be serviced first before INTR (due to higher priority) Case 5 If an INT instruction or an interrupt due to exceptions (internal interrupts) happens at the exact moment an INTR happens, internal interrupt will be serviced first It is because the at the end of each instruction cycle, processor checks for internal interrupt before external interrupt In this case INT is detected first since the ISR of INT disables IF, INTR will not be detected 32 Interrupt cases Case 6 If an INT instruction or an interrupt due to exceptions (internal interrupts) happens at the exact moment an NMI happens, internal interrupt will be accepted first It means processor will clear the IF flag, push flag and return address to stack and load PC and CS from IVT Since NMI is non-maskable, when processor checks for external interrupt, it will then detect NMI The NMI is accepted, thus pushing the current PC, CS and flag register to stack and loading the ISR vector of NMI from IVT In this case NMI will get serviced first before the INT 33 Multiple Peripheral Interrupts oMost computers have multiple peripherals, and processor has a single INTR signal, how to support this oThis may appear as single issue which can be solved by ORing the interrupt signals from the peripherals (assuming they all give active high reset) oBut the issue is with the interrupt type (IRQ number) during interrupt ACK cycle oIf multiple peripherals drive the data bus with IRQ number, it will be disastrous oAlso the IRQ number for peripherals should be somewhat dynamic 34 Multiple Peripheral Interrupts oThere should be some provision to decide them at hardware system design time or software design time or in the best case at run-time oWe can not always fix them at the peripheral design time oThat means there should be some smart bridge sitting in between the processor and peripherals concatenating the interrupts from the peripherals and handling the IRQ oIt is a (programmable) interrupt controller (PIC) oOne of the most popular one used on 8086 (and even later processor) based systems was the Intel 8259 PIC 35 Summary o 8086 supports 2 external interrupt inputs, NMI and INTR o It supports 256 software interrupts through INT instructions (INT 0 to INT 255) o At most 8086 can support 256 interrupts since the IVT can store only the addresses (vectors) of 256 interrupts o Software or NMI interrupts cannot be masked (disabled) o INTR interrupt can be masked using the IF flag in the flag register o When NMI interrupt happens, the ISR address is directly taken from the IVT (vector no.2, physical address 0x8 and 0xA) o When INTR interrupt happens, processor initializes an interrupt ack cycle and the type (IRQ number) should be available of the lower byte of data bus during second cycle. Using this ISR vector is taken from IVT 36 37