Polling vs Interrupts

Polling Vs Interrupts

• Processors interface with a variety of peripherals.
• Peripherals are often much slower than the processor executing instructions.
• Peripherals with mechanical parts particularly exemplify this.
• Peripherals sometimes require external data from sensors or networks, slowing them down further.

Polling Inefficiency

• Polling is illustrated by a processor sending data to a printer.
• The processor must determine if the printing was successful or if an error occurred, such as a paper jam.
• To ascertain the printer's status, the processor continuously reads a control signal like the ACK signal.
• This continuous status reading is called polling.
• Polling is highly inefficient because the processor is stuck reading status and cannot perform other tasks.

Interrupt Efficiency

• Instead of continuously checking the peripheral, interrupts allow the peripheral to inform the processor when it needs attention.
• As an example, the processor sends data to the printer and continues with other jobs.
• The printer will request attention in case it successfully completes the job or if an error occurs.
• Interrupts make systems more efficient as they enable concurrent operations.
• The processor is not stuck with one peripheral, and multiple peripherals can run in parallel.

Interrupt Implementation and Identification

• The interrupt mechanism can be implemented using a physical signal from a peripheral to the processor as legacy interrupts
• A special data pattern, such as MSI in PCIe, is sent to the processor
• Modern systems use a mix of both methods, such as in USB, where a USB host polls devices and interrupts.
• To distinguish between interrupts from different peripherals, each interrupt has a unique interrupt request number (IRQ number).
• Upon receiving an interrupt, the processor executes a special function called an interrupt service routine (ISR).

8086 Interrupt Sources

• 0x86 processors can receive interrupts externally or internally, via software or exceptions.
• External interrupts arrive through the INTR and NMI pins.
• Software interrupts can be generated using the INT instruction.
• Error conditions, such as division by zero or overflow, generate interrupts.

Actions During an Interrupt

• The 8086 checks for pending interrupts at the end of each instruction cycle.
• Upon detecting a pending interrupt, the stack pointer decrements by 2, and the flag register is pushed onto the stack.
• The 8086 INTR Interrupt input is disabled by clearing the interrupt flag (IF) in the flag register, and the TRAP flag is reset.
• The stack pointer decrements by 2, and the current code segment register contents are pushed onto the stack.
• The stack pointer decrements again by 2, and the current instruction pointer, effectively the address of the next instruction, is pushed.
• A far jump to the start of the ISR occurs.

Actions After ISR Completion

• An IRET instruction should be present in the ISR for returning.
• Upon encountering IRET, the IP is popped from the stack.
• The stack pointer is incremented by 2, and the CS is popped.
• The flag register is popped.
• Execution continues with the next instruction.

Interrupt Vectors and Interrupt Vector Table (IVT)

• The starting address of an ISR is called the interrupt vector.
• Unlike regular procedures, there is no explicit call instruction for ISRs; they are implicitly called when an interrupt occurs.
• Interrupt vectors are stored in the interrupt vector table.
• For 8086, 256 IRQs are supported, allowing up to 256 ISRs.
• Each interrupt vector requires 4 bytes of storage: 2 bytes for the code segment (CS) and 2 for the instruction pointer (IP).
• The total IVT size for 8086 is 1 KB (4B*256).
• The 8086 IVT is stored at a predefined location starting at 0000:0000H up to 0000:03FFH.

Reserved IRQs

• Intel reserves certain IRQs, out of 256, for specific purposes.
• Examples include Type-5 Vector at 016H, Type-4 Vector at 012H, and Divide by 0 Error at 000H.

Interrupt Vector Usage

• To use an IRQ number, determine the IVT offset by multiplying the IRQ number by 4.
• The IP and CS values are loaded from the IVT.
• The ISR starts.

Type-0 Interrupt (IRQ-0 Interrupt)

• This interrupt is automatically raised upon a division by zero exception.
• The ISR IP offset should be at address 0x00000, and CS should be at 0x00002.
• If the ISR is not explicitly written or the IVT is not properly initialized, system behavior will be undefined.
• When this exception occurs, the processor will blindly start executing from the address specified in the IVT.

Type-1 Interrupt (IRQ-1 Interrupt)

• Also referred to as the trap interrupt.
• Used mostly for debugging, such as when using the trace option.
• The interrupt is raised at the end of an instruction if the TRAP flag bit is set.
• Once this interrupt occurs, the processor fetches the ISR address from 0x00004 (IP) and 0x00006 (CS) after pushing the flag, CS, and IP of the next instruction to the stack.

Clearing Trap Flag

• 8086 does not have a single instruction to set or clear the TRAP flag bit
• It is done with the help of stack memory
• To clear trap flag perform AND operation with 0xFEFF.

Type-2 Interrupt (IRQ-2 Interrupt)

• Triggered by a low-to-high transition (positive edge-triggered) on the NMI pin.
• Type 2 interrupt response cannot be disabled or masked.
• Very system-critical signals are connected to NMI.
• A power good signal can be connected to back up system status (registers and RAM) to non-volatile memory upon power failure.
• The system can be powered with a super capacitor for this purpose.

Type-3 Interrupt (IRQ-3 Interrupt)

• Produced by executing the INT 3 instruction.
• The main use of the type 3 interrupt is to implement a breakpoint
• They are very useful during debug
• INT 3 is a single byte instruction (CCH).
• When the program is asked to run until a certain address.
• The instruction there is temporarily replaced with INT 3.
• the processor executes instructions until the breakpoint and calls the ISR for INT 3
• Actions that are taken then depends on ISR may print all register contents.

Type-4 Interrupt (IRQ-4 Interrupt)

• Referred to as the overflow interrupt.
• Overflow can occur when performing arithmetic operations.
• Has significance only if operands are unsigned.
• There are no special indications for ADD and SUB if operands are signed or unsigned.
• If overflow flag is set, JO or JNO instructions may be used.
• INTO instruction (interrupt on overflow instruction can be used after the arithmetic operation
• If there is no overflow, INTO does nothing but If there is overflow, it starts interrupt handling

Software Interrupts

• Software interrupts can be raised using the INT instruction.
• The IRQ number (type) follows INT; for example: INT 21H.
• IRQ can be from 0 to 255.
• Similar to previously discussed interrupts, the ISR address is taken from the IVT.
• INT instruction can raise even the predefined instruction
• For example, INT 0 calls the same ISR define for division by 0 error.

INTR Interrupts (Hardware Interrupts)

• Hardware peripherals can interrupt 8086 by sending a high signal on the INTR pin.
• INTR is a level-triggered interrupt.
• Unlike NMI, INTR can be masked or disabled.
• The processor responds only if the IF (Interrupt Flag) bit in the flag register is set.
• Instructions for setting or clearing the flag bit, STI and CLI respectively.
• When 8086 is reset, the IF flag is set to 0 by default so peripherals can be set up before interrupts happen

INTR Clearing

• IF flag is automatically cleared when an ISR is called.
• This prevents interrupt nesting.
• Software can re-enable the IF bit within the ISR if nesting is desired or supportable.
• Because a flag register is pushed to stack, the IF bit is restored to its original value after ISR completion.
• The 8086 executes 2 interrupt acknowledge machine cycles by asserting INTA' signal in response to INTR.
• During the second cycle, with INTA' de-asserted, the interrupting peripheral places the IRQ number on the lower byte of the data bus.
• Using this, 8086 fetches the ISR start address from IVT and enters the ISR.
• The IRQ number here can be anything between 0–255.
• A peripheral may choose to put 0 as the IRQ number and execute the ISR corresponding to a divide by 0 error.

Interrupt Priority

• Interrupt handling when multiple interrupts happen simultaneously.
• The interrupt with the higher priority is serviced first.
• Internal interrupts and external interrupts.
• Interrupt priority from highest to lowest: divide error/INT n/INTO, NMI, INTR, Single Step.

Cases

• Two software interrupts cannot happen simultaneously and are processed in the order that they are handled
• When IF flag is cleared at beginning of the ISR, INTR won't be detected during the run
• When NMI occurs and processor is already in ISR, NMI will be serviced first even if the system is handling the ISR for an NMI
• If INTR and NMI occurs simultaneously, NMI will be serviced and INT can cause interrupt nesting
• If internal interrupts (INT instructions) and INTR happens at once, INT instructions will be serviced first so INTR will not be detected

Multiple Peripheral Interrupts

• Issue of the type (IRQ number) during the cycle ACK
• Solution can be hardware/software design or runtime environment
• Programmable) Interrupt Controller (PIC) can be used
• Intel 8259 PIC is very popular

Summary Points

• The 8086 has two external interrupt inputs: NMI and INTR.
• Up to 256 software interrupts through INT instructions (INT 0 to INT 255).
• Up to 256 interrupts can be supported since the IVT can store that amount of vector addresses.
• Software or NMI cannot be masked, while INTR can via the IF flag.
• NMI ISR addresses are taken from the physical address 0x8 and 0xA.
• In other words the interrupt type is IRQ for the lower byte during runtime.