Introduction to Assembly Language PDF

Module 4: Introduction to Assembly Writing an assembly language program is a complicated task, Language particularly for a beginner....

Module 4: Introduction to Assembly Writing an assembly language program is a complicated task, Language particularly for a beginner. -​ We make this daunting task simple by hiding those Assembly language is the most basic programming language irrelevant details. available for any processor. -​ We achieve this by (1) providing special I/O routines -​ With AL, a programmer works only with operations and (2) defining a basic assembly language template. implemented directly on the physical CPU. -​ Assembly language lacks high-level conveniences Facilitating Input/Output such as variables and functions, and it is not portable We rarely write programs that do not input and/or output data. between various families of processors. -​ High-level languages provide facilities to input and -​ Nevertheless, assembly language is the most output data. powerful computer programming language available, -​ For example, C provides scanf and printf functions to and it gives programmers the insight required to write input and output data, respectively. effective code in high-level languages. -​ Typically, high-level languages can read numeric data (integers, floating-point numbers), characters, and Lesson 1: Programming with Assembly Language strings What is Assembly Language The assembly language, however, does not provide a Each personal computer has a microprocessor that manages convenient mechanism to input/output data. the computer's arithmetical, logical, and control activities. -​ The operating system provides some basic services -​ Each family of processors has its own set of to read and write data, but these are limited. instructions for handling various operations, such as -​ For example, there is no function to read an integer getting input from the keyboard, displaying from the keyboard. information on the screen, and performing various other jobs. To facilitate I/O in assembly language programs, it is necessary -​ These sets of instructions are called 'machine to write the required procedures. language instructions'. -​ We developed a set of I/O routines to read and display signed integers, characters, and strings. A processor understands only machine language instructions, -​ Each I/O routine call looks like an assembly language which are strings of 1's and 0's. instruction. -​ However, machine language is too obscure and -​ This is achieved by using macros. complex for use in software development. -​ Each macro call typically expands to several -​ So, the low-level assembly language is designed for a assembly language statements and includes a call to specific family of processors that represent various an appropriate I/O procedure. instructions in symbolic code and a more understandable form. These two functions are separated into two I/O files: ​ The io.mac file contains the macro definitions for the Advantages of Assembly Language I/O routines. Understanding assembly language makes one aware of − ​ The io.o contains the I/O procedures that perform the -​ How programs interface with OS, processor, and operation. This file is needed by the linker. BIOS. -​ How data is represented in memory and other Input/Output Routines external devices. The I/O routines facilitate reading and displaying characters, -​ How the processor accesses and executes strings, and integers. These include: instructions. -​ How instructions access and process data. Character I/O -​ How a program accesses an external device. Two macros are defined as input and output characters: PutCh and GetCh. The format of PutCh is Other advantages of using assembly language are − PutCh source -​ It requires less memory and execution time. where the source can be any general-purpose, 8-bit register, a -​ It allows hardware-specific complex jobs more easily. byte in memory, or a character value. -​ It is suitable for time-critical jobs. -​ It is most suitable for writing interrupt service routines Note that the memory operands should be in []. The format of and other memory resident programs. GetCh is GetCh destination Assembly language depends upon the instruction set and the where the destination can be either an 8-bit register or a byte processor's architecture. in memory. Some examples are -​ In this tutorial, we focus on Intel-32 processors like GetCh DH Pentium. GetCh [response] In addition, a nwln macro is defined to Some examples are: display a new line (e.g., \n in C). It takes no operands. PutInt AX PutInt [sum] String I/O GetInt CX PutStr and GetStr are defined to display and read strings, GetInt [count] respectively. -​ The strings are assumed to be in a NULL-terminated Long integer I/O is similar except that the source and format. destination must be a 32-bit register or a memory -​ That is, the last character of the string must be the doubleword (i.e., 32 bits). NULL ASCII character, which signals the end of the -​ For example, if the total is a 32-bit number in memory, string. we can display it by PutLint [total] The format of PutStr is and read a long integer from the keyboard into total by PutStr source GetLint [total] where source is the name of the buffer containing the string to be displayed. For example, PutStr message displays the string stored in the buffer message. -​ If the buffer does not contain a NULL-terminated string, a maximum of 80 characters are displayed. The format of GetStr is, GetStr destination [,buffer_size] where destination is the buffer name in which the string is stored. -​ The input string can be terminated by return. -​ You can also specify the optional buffer_size value. -​ If not specified, a buffer size of 81 is assumed. -​ Thus, in the default case, a maximum of 80 characters is read into the string. -​ If a value is specified, (buffer_size−1) characters are read. -​ The string is stored as a NULL-terminated string. -​ You can backspace to correct the input. Here are some examples: GetStr in_string; reads at most 80 characters GetStr TR_title,41; reads at most 40 characters Numeric I/O There are four macros to perform integer I/O: two are defined for 16-bit integers and the remaining two for 32-bit integers. Lesson 2: The Assembly Process 16-bit integer I/O routines—PutInt and GetInt. The formats of Assembler/compiler: a program that executes on your these routines are computer system. PutInt source -​ It translates programs from one form (source code) to GetInt destination another (machine code). where the source and destination can be a 16-bit register or a -​ A typical x86 assembler, for example, would read memory word. lines of text with x86 instructions, parse each -​ PutInt displays the signed number at the source. It statement, and then write the binary equivalent of suppresses all leading 0’s. each instruction directly to memory or to a file for later -​ GetInt reads a 16-bit signed number into the execution. destination. You can backspace while entering a number. The valid range of input numbers is −32,768 The assembly consists of 4 main steps: to +32,767. 1.​ Assembling the source code into an object file -​ If an invalid input (such as typing a non-digit 2.​ Linking the object file with other modules or libraries character) or out-of-range number is given, an error into an executable program message is displayed, and the user is asked to type a 3.​ Loading the program into memory valid number. 4.​ Running the program  The actual value is fixed up by the linker after all the object files are combined (for example, io.o in our example). -​ Macro definitions are also expanded. For example, the PutStr on line 186 is expanded on lines 187 through 190. The List File Program 2 gives a simple program that reads two signed integers from the user and displays their sum if there is no overflow; otherwise, it displays an error message. -​ The input numbers should be in the range −2,147,483,648 to +2,147,483,647, which is the range of a 32-bit signed number. -​ The program uses PurStr and GetLInt to prompt and read input numbers (see lines 22, 23 and 26, 27). -​ The sum of the input numbers is computed on lines 30–32. -​ If the resulting sum is outside the range of a signed 32-bit integer, the overflow flag is set by the add instruction. -​ In this case, the program displays the overflow message (line 36). -​ If there is no overflow, the sum is displayed (lines 42 and 43). List File Contents The format of the list file lines is Line# offset machine-code nesting-level source-line Line#: the number of the listing file line numbers. -​ These numbers are different from the line numbers in the source file. Offset: an 8-digit hexadecimal offset value of the machine code for the source statement. -​ For example, the offset of the first instruction (line 187) is 00000000H, and that of the add instruction on line 219 is 00000035H. -​ Source lines such as comments do not generate any offset. machine-code: the hexadecimal representation of the machine code for the assembly language instruction. nesting-level: the level of nesting of “include files” and macros. source-line: a copy of the original source code line. -​ In Program B.3, the number of bytes required for the machine code depends on the source instruction. -​ When operands are in memory like number1, their relative address is used in the instruction encoding.  -​ Macros permit the assembly language programmer to name a group of statements and refer to the group by the macro name. -​ During the assembly process, each macro is replaced by the group of statements that it represents and assembled in place. -​ This process is referred to as macro expansion. -​ We use macros to provide the basic input and output capabilities to standalone assembly language programs. Assembly language statements are entered once per line in the source file. -​ All three classes of the assembly language statements use the same format: [label] mnemonic [operands] [;comment] The fields in the square brackets are optional in some statements. -​ As a result of this format, it is common practice to align the fields to aid the readability of assembly language programs. -​ The assembler does not care about spaces between the fields. Here is an example of an assembly language statement: repeat: inc result ;increment result by 1 -​ The label repeat can be used to refer to this particular statement. -​ The mnemonic inc indicates increment operation to be done on the data stored in memory at a location identified by the result. Lesson 3: Assembly Language Statement Types The following assembler directive defines a constant CR. The Assembly Language Statements ASCII carriage-return value is assigned to it by the EQU Assembly language programs are created out of three directive. different classes of statements. CR EQU 0DH ;carriage-return character 1.​ Statements in the first class tell the processor what to do. In the previous two examples, the label field has two different -​ These statements are called executable forms. instructions, or instructions for short. -​ The label in the executable instruction is followed by a -​ Each executable instruction consists of an colon (:) but not in the directive statement. operation code (opcode for short). -​ Certain reserved words that have special meaning to -​ Executable instructions cause the assembler the assembler are not allowed as labels. to generate machine language instructions. -​ These include mnemonics such as inc and 2.​ The second class of statements provides information EQU. to the assembler on various aspects of the assembly process. The fields in a statement must be separated by at least one -​ These instructions are called assembler space or tab character. directives or pseudo-ops. -​ More spaces and tabs can be used at the -​ Assembler directives are nonexecutable and programmer’s discretion, but the assembler ignores do not generate any machine language them. instructions. 3.​ The last class of statements, called macros, is used It is a good programming practice to use blank lines and as a shorthand notation for a group of statements. spaces to improve the readability of assembly language programs.  -​ We almost always write labels on a separate line unless doing so destroys the program structure. -​ Thus, our first example assembly language statement is written on two lines as repeat: inc result ;increment result by 1 Lesson 4: Linking and loading Assembly and linking: the last steps in the compilation process—they turn a list of instructions into an image of the program’s bits in memory. Instead of writing a single huge file, many assembly language Loading: puts the program in memory so that it can be applications are composed of numerous smaller files. executed. -​ Program modularity may be distinguished by splitting big programs into smaller files. In this section, we survey the basic techniques required for -​ If the software requires library routines, those will assembly linking to help us understand the complete already be preassembled, and it's possible that the compilation and loading process. libraries' assembly language source code won't be sold separately. The function of linkers and assemblers in the compilation process is shown in Figure. Linker: enables a program to be assembled from several -​ By using compilation commands to create an smaller bits. executable program, this process is frequently -​ The linker alters the assembled code to generate the concealed from us. required linkages between files as it works with the object files that the assembler has produced. Compilers: produce human-readable assembly language as the instruction-level program rather than machine code directly. Fig. External references and entry points. -​ The compiler writer is liberated from minutiae unrelated to compilation, such as the instruction format and the precise locations of instructions and data, by generating assembly language instead of binary instructions. Assembler: convert symbolic assembly language statements into object code, which is a bit-level representation of instructions. -​ The assembler handles instruction formats and does some of the labels to address translation. Linker: The last stages in finding the locations of instructions and data are instead carried out by the linker, which creates an executable binary file, because the program may be constructed from several files. -​ But unless the linker occurs to generate the executable immediately in RAM, that file might not always be in the CPU's memory. In the same file, certain labels will both be specified and Loader: the name of the program that loads the program into utilized. memory before running it. -​ As seen in Figure 4.2, additional labels will be specified in a single file but utilized elsewhere. Fig. Program generation from compilation through loading Entry point: the location in the file where a label is declared. External reference: the location in the file where the label is utilized. Loader: the primary responsibility is to resolve external references using the various entry points. Assembler: provides the symbol table along with the object file to the linker because it is necessary for the linker to understand how definitions and references relate to one another.  -​ Even if the entire symbol table is not kept for later debugging purposes, it must at least pass the entry points. External references: identified in the object code by their relative symbol identifiers. Two steps make up the linker's operation: 1.​ It starts by figuring out where each object file's start address is located. -​ By setting parameters when the loader is started or by producing a load map file that specifies the order in which files are to be loaded into memory, the user can determine the order in which object files should be loaded. -​ It is simple to determine the beginning address of each file given the sequence in which the files should be inserted into Debug Address Registers (DR0 – DR3) memory as well as the size of each object The linear address connected to one of four breakpoint file. circumstances is stored in each of these registers. -​ Bits in DR7 are used to better specify each breakpoint 2.​ At the start of the second phase, the loader merges situation. all symbol tables from the object files into a -​ Regardless of whether paging is enabled or not, the single, large table. debug address registers are functional. -​ The object files are then edited to convert -​ These registers' addresses are linear addresses. relative addresses into addresses. -​ Processor's paging mechanism: converts the -​ To do this, the assembler usually adds linear addresses into physical addresses if paging is additional bits to the object file, allowing the enabled. user to identify the instructions and fields -​ These linear addresses are equivalent to physical that correspond to labels. addresses if paging is not enabled. -​ A user is informed of the problem and the label is undefined if it cannot be in the Debug Control Register (DR7) combined symbol table. Debug Control Register: both help to define the debug conditions and selectively enable and disable those conditions. Lesson 5: Register-level debugging -​ For each address in registers DR0-DR3, the Debug features: managed by six 80386 registers. corresponding fields R/W0 through R/W3 specify the -​ Variants of the MOV (Move to/from Special Registers) type of action that should cause a breakpoint. instruction are used to access these registers. -​ Either the source operand or the destination operand The processor interprets these bits as follows: can be a debug register. ​ 00 -- Break on instruction execution only -​ The MOV instructions that access the debug registers ​ 01 -- Break on data writes only can only be performed at privilege level zero since ​ 10 -- undefined they are privileged resources. ​ 11 -- Break on data reads or writes but not instruction -​ When operating at any other privilege level, fetches attempting to read or write the debug registers results in a general protection exception. Fields LEN0 through LEN3 specify the length of data item to be monitored. Figure 23 - Debug Registers. -​ A length of 1, 2, or 4 bytes may be specified. The values of the length fields are interpreted as follows: ​ 00 -- one-byte length ​ 01 -- two-byte length ​ 10 -- undefined ​ 11 -- four-byte length If RWn is 00 (instruction execution), then LENn should also be 00. Any other length is undefined. The four address breakpoint conditions are only enabled when -​ To avoid any confusion in identifying the next debug the low-order eight bits of DR7 (L0 through L3 and G0 through exception, the debug handler should move zeros to G3) are set to ON. DR6 immediately before returning. -​ The local (L0 through L3) and global (G0 through G3) levels of enablement exist. Breakpoint Field Recognition -​ To prevent undesirable breakpoint circumstances in The linear address and LEN field for each of the four the new task, the processor automatically resets the breakpoint conditions define a range of sequential byte local enable bits at each task changeover. addresses for a data breakpoint. -​ The global enable bits can be used for conditions -​ The LEN field permits the specification of a one-, that apply to all tasks because a task switch does not two-, or four-byte field. cause them to be reset. -​ Two-byte fields must be aligned on word boundaries (addresses that are multiples of two) and four-byte The processor's "precise data breakpoint match" function is fields must be aligned on doubleword boundaries controlled by the LE and GE bits. (addresses that are multiples of four). -​ When LE or GE are either set, the CPU slows down -​ These requirements are enforced by the processor; it execution so that data breakpoints are noted on the uses the LEN bits to mask the low-order bits of the causing instruction. addresses in the debug address registers. -​ When data breakpoints are armed, it is advised that -​ Improperly aligned code or data breakpoint addresses one of these bits be set. will not yield the expected results. -​ At a task changeover, the CPU does not clear GE but does clear LE. A data read or write breakpoint is triggered if any of the bytes participating in a memory access is within the field Debug Status Register (DR6) defined by a breakpoint address register and the Debug Status Register: permits the debugger to determine corresponding LEN field. which debug conditions have occurred. -​ Table 12-1 gives some examples of breakpoint fields with memory references that both do and do not When the processor detects an enabled debug exception, it cause traps. sets the low-order bits of this register (B0 through B3) before entering the debug exception handler. To set a data breakpoint for a misaligned field longer than one -​ Bn is set if the condition described by DRn, LENn, byte, it may be desirable to put two sets of entries in the and R/Wn occurs. (Note that the processor sets Bn breakpoint register such that each entry is properly aligned, regardless of whether Gn or Ln is set. If more than and the two entries together span the length of the field. one breakpoint condition occurs at one time and if the breakpoint trap occurs due to an enabled condition Instruction breakpoint addresses must have a length other than n, Bn may be set, even though neither Gn specification of one byte (LEN = 00); other values are nor Ln is set.) undefined. -​ The processor recognizes an instruction breakpoint BT bit: associated with the T-bit (debug trap bit) of the TSS address only when it points to the first byte of an (refer to 7 for the location of the T-bit). instruction. If the instruction has any prefixes, the -​ The processor sets the BT bit before entering the breakpoint address must point to the first prefix. debug handler if a task switch has occurred and the T-bit of the new TSS is set. Table 14 – Breakpoint field recognition examples -​ There is no corresponding bit in DR7 that enables and disables this trap; the T-bit of the TSS is the sole enabling bit. BS bit: associated with the TF (trap flag) bit of the EFLAGS register. -​ The BS bit is set if the debug handler is entered due to the occurrence of a single-step exception. -​ The single-step trap is the highest-priority debug exception; therefore, when BS is set, any of the other debug status bits may also be set. BD bit: set if the next instruction will read or write one of the eight debug registers and ICE-386 is also using the debug registers at the same time. Note that the bits of DR6 are never cleared by the processor. Module 5: General Architecture Issues management and programming. It is a big issue in Computer architecture: forms the bridge between application computer design. needs and the capabilities of the underlying technologies. 6.​ Multiple threads: A computer with several threads -​ As application demands change and technologies should be able to multi-tasking and multi-processing. cross various thresholds, computer architects must 7.​ Shared memory: If there are several processes to be continue innovating to produce systems that can executed at a time, then all the processes share the deliver needed performance and cost-effectiveness. same memory space. -​ It should be managed in a specific way so that collision does not happen. Lesson 1: Limitations and Design Issues 8.​ Disk access: Disk management is the key to computer design. There are several issues with disk Computer Architecture: discusses the computer hardware access. components, their organization and architecture, the way the -​ It may be possible that the system does not hardware components operate, and the way they are support multiple disk access. connected to form the computer system. 9.​ Better performance: It is always an issue. A designer always tries to simplify the system for better Computer design: concerned with the hardware design of the performance in reducing power and less cost. computer. -​ Once the computer specifications are formulated it is the task of the designer to develop hardware for the Lesson 2: Optimization Methods system. -​ Computer design is concerned with the determination To improve the design issues, these optimization methods will of what hardware should be used and how the parts help overcome them: should be connected. 1.​ Increasing the speed of the data processing -​ This aspect of computer hardware is sometimes hardware: The assumption of infinite speed data is referred to as computer implementation. real. -​ To overcome this, data processing speed Computer architecture: is concerned with the structure and can be improved by increasing the speed of behavior of the computer as seen by the user. the data processing hardware, or by -​ It includes the information formats, the instruction set, improving the efficiency of the data and techniques for addressing memory. processing algorithms. -​ To produce better results, the assumption of Architectural design of a computer system: concerned with infinite speed data can be replaced with the the specifications of the various functional modules, such as assumption of finite speed data. processors and memories, and structuring them together into a -​ This will allow for more accurate processing computer system. times and avoid delays. Computer design: an integration of the fields of electrical the information handling rate can be improved by speeding engineering, programming, and computer architecture. up the information handling equipment or by working on the -​ At the core of computer design is a fundamental proficiency of the information handling calculations. understanding of the hardware and software -​ To enhance results, the presumption of endless speed components that make up computers and computer information can be supplanted with the suspicion of systems, as well as how they're designed, configured, limited speed information. and constructed. -​ This will consider more precise handling times and keep away from delays. The following are the issues in computer design: -​ One of the primary justifications for why the suspicion 1.​ Assumption of infinite speed of boundless speed information can prompt 2.​ Assumption of infinite Memory: Like the speed of postpones in handling is because it doesn't take into the computer, memory also can’t be assumed infinite. account the investment it takes for the information to Storage is always finite, and this is an issue in be moved to start with one area and then onto the computer design. next. 3.​ Speed mismatch between memory and processor: -​ For instance, if data is being transferred from a Sometimes it is possible that the speed of memory capacity gadget to a PC's RAM, the speed of the and processor does not match. A mismatch between information move will be restricted by the speed of the memory and processor leads to create problems in stockpiling device and the PC's RAM. This can create designing. setbacks if the information move is slow. 4.​ Handling of bugs and errors: Bugs and errors lead to the failure of the computer system. Sometimes 2.​ Use a computer with a large amount of memory: these errors may be more dangerous. Another way to overcome this issue is to use a 5.​ Multiple processors: Designing a computer system database. with multiple processors leads to the huge task of  -​ This would allow for data to be stored in a 2.​ remember that both memory and processing are way that is not limited by memory. It is also important and that they both need to work well to possible to use a cloud storage system and produce better results. be stored in a remote location that is not 3.​ keep both memory and processing working together limited by memory. by using techniques such as mnemonic devices. -​ The assumption of infinite memory data can 4.​ practice using both memory and processing to keep be a real or imagined issue. them both working well. -​ It is possible to overcome this issue 5.​ be patient when using both memory and processing, by using a computer with a large as it can take some time to get used to using both amount of memory, using a together. database, or using a cloud storage system. Module 6: The Intel 8088 -​ Assuming that data can be stored infinitely is a misconception. Over time, data will Intel 8088: a type of microprocessor that is part of the Intel degrade and become corrupted. 8086 series of microprocessors. -​ To overcome this, data needs to be -​ It was released in 1979 and has identical architecture backed up and stored in a secure to the Intel 8086, except for reduced external data bus location. width size from 16-bit to 8-bit. -​ In addition, assuming that data can be accessed instantly is also a misconception. Being an 8-bit microprocessor, the Intel 8088 requires two -​ Data retrieval can take time, cycles to process 16-bit data. depending on the size and location -​ The Intel 8088 has a clock speed from 5-10 MHz, with of the data. 16-bit registers, a 20-bit address bus, and a 16-bit -​ To overcome this, data needs to be external data bus, and supports 1 MB of memory. well-organized and stored in an -​ The Intel 8088 also supports the Intel 8087 numeric accessible location. There is a co-processor that enables it to recognize and process limited amount of storage space floating point data and instructions. available, so data needs to be managed carefully. The original Intel 16-bit CPU was the 8086. -​ It was designed to be backward-compatible at the Overcoming this misconception requires understanding the assembler level with Intel’s 8-bit CPU, the 8080. limits of storage space and managing data accordingly. -​ The 8088 is a version of the 8086 with an 8-bit data -​ This can be done by deleting unnecessary data, bus. compressing data to save space, and using cloud -​ The 8088 was used in the original IBM PC and its storage to offload data. many clones. -​ Assuming that data can be stored infinitely can lead to -​ Later versions of the 8086 include the i386 which problems. For example, if data is not managed extends the data and address registers to 32 bits and properly, it can fill up storage space and lead to data includes support for memory protection and virtual loss. memory. -​ In addition, if data is not compressed, it can take up a lot of space and cause performance issues. 3.​ Be aware of the potential for changes in memory and processing speed as we age: We can take steps to improve our memory and processing speed. -​ There are several exercises and games that can help to improve these skills. We can also use tools to help us keep track of information and organize it in a way that makes it easier to process. -​ By taking these steps, we can overcome the Lesson 1: Organization and Architecture assumption that memory and processing always operate at the same speed, and we Below is a block diagram of the organizational layout of the can improve our ability to recall memories Intel 8088 processor. and understand new information. -​ It includes two main sections: the Execution Unit (EU) and the Bus Interface Unit (BIU). There are a few things that can be done to produce better results when it comes to memory and processing. EU: takes care of the processing including arithmetic and logic. 1.​ Make sure that both memory and processing are BIU: controls the passing of information between the working optimally. processor and the devices outside of the processor such as General Registers memory, I/O ports, storage devices, etc. These registers are categorized into two sets: data and address. -​ The data registers are for calculations; the address registers contain memory addresses and are used to point to the locations in memory where data will be retrieved or stored. The diagram shows four pairs of registers – AH, AL, BH, BL, CH, CL, DH, and DL. -​ These are the data registers. -​ Each of these registers is 8 bits long. Each pair can also operate as a single 16-bit register. -​ AH and AL can operate as a pair referred to as AX (Accumulator Register). -​ BH and BL form a pair BX (Base Register), -​ CH and CL form a pair CX (Counter Register), and DH and DL form a pair referred to as DX (Data Register). The data registers in the block diagram are the address registers: SP, BP, DI, and SI. -​ These are officially referred to as the pointer (SP and BP) and index registers (DI and SI). -​ These registers are used with the segment registers to point to specific addresses in the processor’s memory space. -​ SP is the stack pointer that points to the “top plate”, or the last piece of data placed on the stack. -​ BP (base pointer), SI (source index), and DI (destination index) are all pointers that the programmer has for their use. The Flags Flag registers: show the status of the task. -​ It is a Special Purpose Register, an 8-bit register, but only 5-bit is used for any operation. -​ The flag becomes set or reset after arithmetic and logical operation. The Flags are categorized into two sets: 1.​ Control Flags (TF, DF, IF) – used to control how the processor runs and are typically controlled by the user’s software. 2.​ Static Flags (OF, SF, ZF, AF, PF, CF) – usually set by the previous operations. Arithmetic Logic Unit: It is the computation portion of the Execution Unit. -​ Any time arithmetic or logic needs to be performed on numbers, the numbers are sent from the general registers to the Arithmetic Logic Unit, the ALU performs the function, and the result is sent back to the general registers. Execution Unit Control System: is a set of gates that control the timing, and passing of data, and other items within the execution unit.  -​ It does not necessarily know the details of the operation, but its plans what happens, where it happens, and when. Instruction Pointer: can be found toward the bottom of the group of registers in the center of the Bus Interface Unit. -​ It is an address register like the Execution unit’s SP, BP, DI, and SI registers. -​ However, its purpose is different. The IP points to the next instruction to execute from memory. Segment Registers: In the center of the Bus Interface Unit section of the processor organizational block diagram is a set of registers labeled CS, DS, SS, and ES. -​ These four registers are the segment registers used in conjunction with the pointer and index register to store and retrieve items from the memory space. Pipelining: It is a process of arrangement of hardware elements of the microprocessors so that their overall performance is increased. -​ Simultaneous execution of more than one instruction takes place in a pipelined processor. Instruction Queue: the mechanism in the Intel 8088 processor that handles the pipelining function. Lesson 2: Assembly Language Programming The operand format is destination, source, e.g., MOV AX,13H loads AX with 19. -​ The assembler keeps track of the type of symbol and uses it to select immediate or direct addressing. Like most programming languages, assembly language source This can be changed by using the OFFSET operator to convert code must follow a well-defined syntax and structure. a memory reference to a 16-bit value. The following is a description of the fields of an assembly For example: language file. MOV BX, COUNT ; load value of COUNT 1.​ Label Field: A label is used to associate the memory MOV BX, OFFSET COUNT ; load location of COUNT address of a specific line of code or a memory location with a text string. (Remember, those humans Hex and binary constants are indicated by using an H or B like to see words, not numbers.) suffix after the number. -​ A leading 0 must be added if the first digit of a hex There are some rules it must follow: constant is not a digit. -​ Labels must begin in the first column with an alphabetic character Example -​ It must not be a reserved string (e.g., it cannot be an This is a simple program that demonstrates the main features assembly language command) of the 8088 instruction set. It uses the INT operation to invoke -​ Labels must not be redefined (reused) MS-DOS to write characters to the screen. -​ Separated (delimited) from fields that come after it by a colon 2.​ Instruction or Opcode Field: The instruction field contains the assembly language commands that the processor is supposed to follow to run a program. The command field must follow these rules: -​ Cannot be in first column. -​ Must be an opcode (processor instruction) or pseudo-op code (assembler instruction).  3.​ Operand field: contains the data that the assembly -​ By structuring memory into relocatable areas of language instructions use to run. similar characteristics and by automatically selecting -​ This includes addresses, constants, register segment registers, programs are shorter, faster, and names, etc. more structured. -​ There is a link to a site later on this page that describes some of the guidelines operands Word (16-bit) operands can be located on even or odd address must follow. boundaries. -​ For address and data operands, the least significant 4.​ Comment Field: The ways to represent comments in byte of the word is stored in the lower-valued address assembly language differ from assembler to location and the most significant byte in the next assembler. higher address location. -​ For most assemblers, comments begin after -​ The BIU will automatically execute two fetch or write opcode/operand with a semi-colon. cycles for 16-bit operands. -​ The assembler ignores everything followed by the comment character until a carriage Memory Segment Segment Selection Rules return/line feed (CR/LF). Reference Register Used Used Lesson 3: Memory Organization and Use Instructions CODE (CS) Automatic with all instruction prefetch. Stack STACK (SS) All stack pushes and pops. Memory references relative to BP base register except data references. Local Data DATA (DS) Data references when: relative to stack, destination of string operation, or explicitly overridden. External EXTRA (ES) Destination of string (Global) Data operations: explicitly selected using a segment override. Locations from addresses FFFF0H through FFFFFH are reserved for operations including a jump to the initial system initialization routine. -​ Following RESET, the CPU will always begin The processor provides a 20-bit address to memory which execution at location FFFF0H where the jump must locates the byte being referenced. be located. -​ The memory is organized as a linear array of up to 1 -​ Locations 00000H through 003FFH are reserved for million bytes, addressed as 00000(H) to FFFFF(H). interrupt operations. -​ The memory is logically divided into code, data, extra -​ Four-byte pointers consisting of a 16-bit segment data, and stack segments of up to 64K bytes each, address and a 16-bit offset address direct program with each segment falling on 16-byte boundaries (See flow to one of the 256 possible interrupt service Figure 3). routines. -​ The pointer elements are assumed to have been All memory references are made relative to base addresses stored at their respective places in reserved memory contained in high-speed segment registers. prior to the occurrence of interruptions. -​ The segment types were chosen based on the addressing needs of the programs. -​ The segment registers to be selected are automatically chosen according to the rules of the following table. -​ All information in one segment type shares the same logical attributes (e.g., code or data).