FA24 05-1 TIMER (PART1-PERIODIC MODE) V2.0 PDF

General Purpose Timer Module (GPTM) Part 1: Timer in Periodic Mode MET2304 (FA24) V1.9 Applications of Timers In embedded applications, time can be represented by the count of a Timer. Timers form an integral part microcontroller applications in embedded...

General Purpose Timer Module (GPTM) Part 1: Timer in Periodic Mode MET2304 (FA24) V1.9 Applications of Timers In embedded applications, time can be represented by the count of a Timer. Timers form an integral part microcontroller applications in embedded systems & programming. Many tasks or applications would be difficult to implement without use of Timers. Timers in embedded systems are used for: Task scheduling (through periodic interrupts). Pulse period or width measurements. Event counting. Elapsed time determination between events. Waveform generation. Frequency & duty cycle measurement of periodic signals. …. MET2304 (FA24) 2 TM4C123G Timers In the Tiva TM4C123G, the Timers are called General-Purpose Timer Modules (GPTM). There are total of: Six 16/32-bit GPTM modules, & Six 32/64-bit GPTM modules. For MET2304, we will focus on the 16/32 bit GPTM modes. Total of six 16/32 bit Timers: Timer 0 to Timer 5. Each 16/32-bit Timer block contains TWO Timers: Timer A & Timer B. Timer A & B are 16-bits timers individually. Each Timer A & B contains its own Counter & can work independently as separate Timers. MET2304 (FA24) 3 TM4C123G Timers A & B Each 16/32-bit GPTM is made up of TWO 16-bit modules (A & B), called Timer A & Timer B. We have the following: Timer 0A & Timer 0B (Base address: 0x4003.0000) Timer 1A & Timer 1B (Base address: 0x4003.1000) Timer 2A & Timer 2B (Base address: 0x4003.2000) Timer 3A & Timer 3B (Base address: 0x4003.3000) Timer 4A & Timer 4B (Base address: 0x4003.4000) Timer 5A & Timer 5B (Base address: 0x4003.5000) Timer A & Timer B can be programmed to operate independently of each other: They can work as two 16-bit Timers, or, together as one 32-bit Timer. MET2304 (FA24) 4 TM4C123G Timer Pins 16/32-bit GPTM modules: Each Timer has an associated [Timer 0A] bi-directional pin: [Timer 0B] T0CCP0 for Timer 0A [Timer 1A] [Timer 1B] T0CCP1 for Timer 0B. [Timer 2A] T1CCP0 for Timer 1A [Timer 2B] T1CCP1 for Timer 1B. [Timer 3A] T2CCP0 for Timer 2A [Timer 3B] T2CCP1 for Timer 2B. [Timer 4A] [Timer 4B] …. and so on. [Timer 5A] [Timer 5B] CCP is short for ‘Capture Compare PWM’, indicating the Timer modes where the pins are used. CCP pin is not used when Timer is configured in Periodic mode. MET2304 (FA24) 5 TM4C123G Timers (32/64-bits) Similarly, each 32-/64-bit modules is made up of TWO 32- bit modules (A and B), called Timer A and Timer B. Wide Timer 0A & Wide Timer 0B: Base address: 0x4003.6000 Wide Timer 1A & Wide Timer 1B Base address: 0x4003.7000 Wide Timer 2A & Wide Timer 2B Base address: 0x4004.C000 Wide Timer 3A & Wide Timer 3B Base address: 0x4004.D000 Wide Timer 4A & Wide Timer 4B Base address: 0x4004.E000 Wide Timer 5A & Wide Timer 5B Base address: 0x4004.F000 MET2304 (FA24) 6 TM4C123G Timers A & B Signals GPIO pin PMCn (in GPIOPCTL reg) All Timer CCP pins are multiplexed with GPIO pins. MET2304 (FA24) 7 TM4C123G Timer Modes Timers operates in one of the following four modes: Periodic mode / One-shot mode : Timer continues counting UP/DOWN after each timeout (Periodic); Stops when Time-out event reached (One-shot). Input Edge Count or Edge Time: counts UP/DOWN with 16-bit pre-scalar. PWM Mode: Timer used with pre-scalar, counts DOWN only. RTC mode: Timer A & B are concatenated, counter counts UP at 32.768 KHz, reloads after terminal count is reached. Modes in bold will be covered in MET2304 MET2304 (FA24) 8 TM4C123G Timers Note: Pre-scaler is only available when the Timers are used INDIVIDUALLY – not available when Timers are concatenated. Use this table as a reference for the Timer modes. This table will be provided during Quiz/Exam when needed. Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spms376e.pdf, p708) MET2304 (FA24) 9 GPTM Timer Registers Not all registers are listed in the following slides MET2304 (FA24) GPTM Timer Registers Each GPTM module has its own set of Control & Status registers. Some registers are denoted by A & B and they both work in the same manner. Timer Registers can be grouped by functions: Timer Control/Configuration. Timer Count Status. Timer Interrupt Control/Status. … see more details in following slides Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spmu376e.pdf, p726) MET2304 (FA24) 11 GPTM Timer Registers (grouped by functions) Timer Control/Configuration Registers: GPTM Configuration (GPTMCFG) GPTM Control (GPTMCTL) GPTM Mode (GPTMTAMR –Timer A, GPTMTBMR –Timer B ) GPTM Interval Load (GPTMTAILR –Timer A, GPTMTBILR –Timer B ) GPTM Match (GPTMTAMATCHR –Timer A, GPTMTBMATCHR –Timer B ) GPTM Prescale (GPTMTAPR –Timer A, GPTMTBPR – Timer B ) GPTM Prescale Match (GPTMTAPMR -Timer A, GPTMTBPMR -Timer B ) GPTM Prescale Snapshot (GPTMTAPS -Timer A, GPTMTBPS -Timer B ) Timer Count Status Registers: GPTM Timer Register (GPTMTAR –Timer A, GPTMTBR –Timer B ) GPTM Timer Value Register (GPTMTAV –Timer A, GPTMTBV –Timer B ) GPTM Prescale Value Register (GPTMTAPV –Timer A, GPTMTBPV –Timer B ) Timer Interrupt Control/Status Registers: GPTM Interrupt Mask (GPTMIMR) GPTM Masked Interrupt Status (GPTMMIS) GPTM Interrupt Clear (GPTMICR) Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spmu376e.pdf, p726) MET2304 (FA24) 12  Timer Register Map Source: Tiva TM4C123GH6PM Microcontroller Data Sheet MET2304 (FA24) (spmu376e.pdf, p726) 13 Timer Data Structure [file: TM4C123GH6PM7.h] typedef struct { 0x4003.0000 CFG __IO uint32_t CFG; 0x4003.0004 TAMR __IO uint32_t TAMR; 0x4003.0008 TBMR __IO uint32_t TBMR; 0x4003.000C CTL __IO uint32_t CTL; 0x4003.0010 SYNC __IO uint32_t SYNC; 0x4003.0014 RESERVED __I uint32_t RESERVED; 0x4003.0018 IMR __IO uint32_t IMR; 0x4003.001C RIS __IO uint32_t RIS; 0x4003.0020 MIS __IO uint32_t MIS; 0x4003.0024 ICR __O uint32_t ICR; 0x4003.0028 TAILR __IO uint32_t TAILR; 0x4003.002C TBILR __IO uint32_t TBILR; 0x4003.0030 TAMATCHR __IO uint32_t TAMATCHR; 0x4003.0034 TBMATCHR __IO uint32_t TBMATCHR; 0x4003.0038 TAPR __IO uint32_t TAPR; 0x4003.003C TBPR __IO uint32_t TBPR; 0x4003.0040 TAPMR __IO uint32_t TAPMR; 0x4003.0044 TBPMR __IO uint32_t TBPMR; 0x4003.0048 TAR __IO uint32_t TAR; 0x4003.004C TBR __IO uint32_t TBR; 0x4003.0050 TAV __IO uint32_t TAV; 0x4003.0054 TBV 0x4003.0058 RTCPD __IO uint32_t TBV; 0x4003.005C TAPS __IO uint32_t RTCPD; 0x4003.0060 TBPS __IO uint32_t TAPS; 0x4003.0064 TAPV __IO uint32_t TBPS; 0x4003.0068 TBPV __IO uint32_t TAPV; __IO uint32_t TBPV; RESERVED __I uint32_t RESERVED1; 0x4003.0FC0 PP __IO uint32_t PP; } TIMER0_Type; MET2304 (FA24) 14 Timer Data Structure [file: TM4C123GH6PM7.h] #define TIMER0_BASE 0x40030000UL #define TIMER1_BASE 0x40031000UL #define TIMER2_BASE 0x40032000UL #define TIMER3_BASE 0x40033000UL #define TIMER4_BASE 0x40034000UL #define TIMER5_BASE 0x40035000UL #define TIMER0 ((TIMER0_Type *) TIMER0_BASE) #define TIMER1 ((TIMER0_Type *) TIMER1_BASE) #define TIMER2 ((TIMER0_Type *) TIMER2_BASE) #define TIMER3 ((TIMER0_Type *) TIMER3_BASE) #define TIMER4 ((TIMER0_Type *) TIMER4_BASE) #define TIMER5 ((TIMER0_Type *) TIMER5_BASE) MET2304 (FA24) 15 Timer Configuration Registers GPTMCFG, GPTMCTL, GPTMTnMR MET2304 (FA24) Configuration Register (GPTMCFG) Type, Reset Value: R/W, 0x0000.0000 Register configures the global operation of the GPTM module. It sets the GPTM to be in one of the following modes of operation: 32- or 64-bit mode (concatenated timers), or 16- or 32-bit mode (individual, split timers), or Real-Timer-Clock (RTC). GPTMCFG bits definition: Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spmu376e.pdf, p727) MET2304 (FA24) 17 Control Register (GPTMCTL) Type, Reset Value: R/W, 0x0000.0000 Register is used with the GPTMCFG & GMTMTnMR to set the timer configuration & enable other timer features. GPTMCTL for both timers A & B. Output Trigger Enable (TAOTE, TBOTE) can be used to initiate transfers on the ADC module. TAEVENT: Timer A Event Mode TAEN: Timer A Enable TBEVENT: Timer B Event Mode TBEN: Timer B Enable Positive Edge : 0x00 Timer Disabled :0 Negative Edge : 0x01 Timer Enabled :1 Both Edge : 0x03 (Used in Input Capture Modes) (See also next slide …) Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spmu376e.pdf, p737) MET2304 (FA24) 18  Control Register (GPTMCTL) Timer A Timer B MET2304 (FA24) 19 Timer Mode Register (GPTMTAMR, GPTMTBMR) [GPTMTAMR shown here] : For Timer B, register name Type, Reset Value: R/W, 0x0000.0000 is GPTMTBMR and has the same bit definitions. Register configures the GPTM based on the configuration selected in the GPTMCFG register Timer Mode Selection: Timer Count Direction: TAMR, TBMR = 0x1 : One-Shot. TACDIR, TBCDIR = 0 : Count Down TAMR, TBMR = 0x2 : Periodic Timer. (default) TAMR, TBMR = 0x3 : Capture Mode. TACDIR, TBCDIR = 1 : Count Up Timer Capture Mode: (Week 9) TACMR = 0 : Edge-Count Mode. TACMR = 1 : Edge-Time Mode. Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spmu376e.pdf, p729) (See also next slide …) MET2304 (FA24) 20 Timer Mode Register (GPTMTAMR, GPTMTBMR) [GPTMTAMR shown here] Timer A bits definition MET2304 (FA24) 21 Enabling a GPTM Module RCGCTIMER, PRTIMER MET2304 (FA24) Enabling a GPTM Module Before a Timer can be initialized and to be able to access its registers, we need to enable the Clock signal to the module & check that its registers are ready to be accessed. Use RCGCTIMER register to enable the clock to the Timer module. Use PRTIMER register to check if Timer registers are ready to be accessed. Both the RCGCTIMER & PRTIMER registers are part of the set of System Control registers. System Control Registers have base address of 0x400F.E000 MET2304 (FA24) 23 Run Mode Clock Gating Register (RCGCTIMER) Type, Reset Value: R/W, 0x0000.0000 When bit is enabled, Timer is provided a clock & accesses to Timer registers are allowed. When disabled, the clock is disabled to save power & accesses to Timer registers generate a bus fault. R0 = ‘1’: Enable & provide clock to Timer 0. R1 = ‘1’: Enable & provide clock to Timer 1. R2 = ‘1’: Enable & provide clock to Timer 2. R3 =‘ 1’: Enable & provide clock to Timer 3. R4 = ‘1’: Enable & provide clock to Timer 4. R5 = ‘1’: Enable & provide clock to Timer 5. A ‘0’ will disable the corresponding Timer module. Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spms376e.pdf, p338) MET2304 (FA24) 24 GPTM Ready Register (PRTIMER) Type, Reset Value: RO, 0x0000.0000 Check this register bits to be sure Timer module is ready. Bit is ‘1’ => Timer is ready to be assessed. Check upon a power reset, run mode clocking or change in power status. R0 denotes Timer 0. R1 denotes Timer 1. R2 denotes Timer 2. R3 denotes Timer 3. R4 denotes Timer 4. R5 denotes Timer 5. Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spms376e.pdf, p404) MET2304 (FA24) 25 Programming Examples #define SYSCTL_RCGCTIMER_R5 0x00000020 // Timer 5 Run Mode Clock Gating Ctrl #define SYSCTL_RCGCTIMER_R4 0x00000010 // Timer 4 Run Mode Clock Gating Ctrl #define SYSCTL_RCGCTIMER_R3 0x00000008 // Timer 3 Run Mode Clock Gating Ctrl #define SYSCTL_RCGCTIMER_R2 0x00000004 // Timer 2 Run Mode Clock Gating Ctrl #define SYSCTL_RCGCTIMER_R1 0x00000002 // Timer 1 Run Mode Clock Gating Ctrl #define SYSCTL_RCGCTIMER_R0 0x00000001 // Timer 0 Run Mode Clock Gating Ctrl #define SYSCTL_PRTIMER_R5 0x00000020 // Timer 5 Peripheral Ready #define SYSCTL_PRTIMER_R4 0x00000010 // Timer 4 Peripheral Ready #define SYSCTL_PRTIMER_R3 0x00000008 // Timer 3 Peripheral Ready #define SYSCTL_PRTIMER_R2 0x00000004 // Timer 2 Peripheral Ready #define SYSCTL_PRTIMER_R1 0x00000002 // Timer 1 Peripheral Ready #define SYSCTL_PRTIMER_R0 0x00000001 // Timer 0 Peripheral Ready SYSCTL->RCGCTIMER |= SYSCTL_RCGCTIMER_R0; SYSCTL->RCGCTIMER |= SYSCTL_RCGCTIMER_R1 | SYSCTL_RCGCTIMER_R2; while( 0 == (SYSCTL->PRTIMER & SYSCTL_PRTIMER_R0) ); // Timer 0 while( 0 == (SYSCTL->PRTIMER & SYSCTL_PRTIMER_R1) ); // Timer 1 MET2304 (FA24) 26 Periodic Timer Mode GPTMTnMR, GPTMTnILR MET2304 (FA24) GPTM Periodic Mode Note (a) Note (a): Pre-scaler is only available when the Timers are used INDIVIDUALLY – not available when Timers are concatenated. Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spms376e.pdf, p708) MET2304 (FA24) 28 Timer Mode Register (GPTMTAMR, GPTMTBMR) Type, Reset Value: R/W, 0x0000.0000 Timer Count Direction: Timer Mode Selection: TACDIR, TBDIR = 0 : Count TAMR, TBMR = 0x1 : One-Shot. Down (default) TAMR, TBMR = 0x2 : Periodic Timer. TACDIR, TBCDIR = 1 : Count Up TAMR, TBMR = 0x3 : Capture Mode. Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spmu376e.pdf, p729) MET2304 (FA24) 29 Timer Interval Load Register (GPTMTAILR, GPTMTBILR) Type, Reset Value: R/W, 0xFFFF.FFFF When the timer is counting DOWN, this register is used to load the starting countdown value into the Timer. When the Timer is counting UP, this register sets the upper bound for the timeout event. For 16/32-bit mode operation: [16-bit mode]: GPTMAILR is a 16-bit register; upper 16-bits read as 0s. [32-bit mode]: GPTMTAILR is a 32-bit register; upper 16-bits is also presented in GPTMTBILR. TAILR = 32-bit load value [TBILR:TAILR], or 16-bit mode value [TAILR]. Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spms376e.pdf, p756) MET2304 (FA24) 30 GPTM Periodic Mode How do we configure a GPTM Timer to be in Periodic mode? Set in Timer Mode register (TnMR) register, n = A or B for Timer A or Timer B. Set the Timer Mode (TnMR) field (2 bits): 0x2 for Periodic Timer mode (TAMR for Timer A; TBMR for Timer B). How do we configure a GPTM Timer to count UP or DOWN? Set in Timer Mode register (TnMR) register, n = A or B for Timer A or Timer B. Use the Count Direction (TnCDIR) bit: TnCDIR = 1 (Count-UP), TnCDIR = 0 (Count-DOWN). How do we configure a GPTM Timer to be in 16- or 32-bits mode? Set in Configuration register (GPTMCFG)... Check slide 17. // Setup Timer 0A to be in periodic mode, count down, 16 bit timer // Other initialization code may be needed to complete the initialization TIMER0->TAMR &= ~0x03; // 2 bit mask, clear bits TIMER0->TAMR |= 0x02; // set Mode bits to Periodic mode TIMER0->TAMR &= ~(1 value of 0xFFFF.FFFF. It means the Timer has the highest count value possible upon Reset, in both Count-UP & Count-DOWN. Timer counter decrements / increments at the bus clock frequency. MET2304 (FA24) 34 Timer Interrupts GPTMIMR, GPTMRIS, GPTMMIS, GPTMICR MET2304 (FA24) Points to Note on Timer Interrupts Registers involved in Interrupt Processing: IMR: Interrupt Mask register MIS: Mask Interrupt Status RIS : Raw Interrupt Status register ICR: Interrupt Clear register Time-Out Event Interrupt Example: If the TOIM (Time-Out Interrupt Mask) in the IMR register is set, Time-Out interrupt is enabled: When a Time-Out event occurs, the TOMIS bit in the MIS register will be set & an interrupt is triggered. When a Time-out event occurs, the TORIS bit in the RIS will be set. This is irrespective of whether the Time-out event is masked in the IMR. Interrupt needs to be cleared by clearing the corresponding bit in the ICR. For Time-Out event, it will be the TOCINT bit in the ICR register. MET2304 (FA24) 36 Interrupt Mask Register (GPTMIMR) Type, Reset Value: R/W, 0x0000.0000 [Timer B Mask] [Timer A Mask] Register allows software to enable/disable GPTM interrupts. Setting a bit enables the corresponding interrupt, while clearing a bit disables it. TATOIM, TBTOIM: Timer Time-Out Interrupt Mask CAMIM, CBMIM: Timer Capture Mode Match Interrupt Mask CAEIM, CBEIM: Timer Capture Mode Event Interrupt Mask TAMIM, TBMIM: Timer Match Interrupt Mask RTCIM: Real-Time-Clock Interrupt Mask Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spms376e.pdf, p745) MET2304 (FA24) 37 Mask Interrupt Status Register (GPTMMIS) Type, Reset Value: R0, 0xFFFF.FFFF [Timer B Intr Status] [Timer A Intr Status] Register show the timer interrupts status. If an interrupt is unmasked in GPTMIMR, & there is an event that causes the interrupt to be asserted, the corresponding bit is set. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. TATOMIS, TBTOMIS: Timer Time-Out Interrupt status CAMMIS, CBMMIS: Timer Capture Mode Match Interrupt status CAEMIS, CBEMIS: Timer Capture Mode Event Interrupt status TAMMIS, TBMMIS: Timer Match Interrupt status RTCMIS: Real-Time-Clock Interrupt status Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spms376e.pdf, p751) MET2304 (FA24) 38 Raw Interrupt Status Register (GPTMRIS) Type, Reset Value: R0, 0x0000.0000 For 32/64-bit Timer [Timer B Status] [Timer A Status] Register shows status of the GPTM's internal interrupts. Status bits are set whether or not the interrupt is masked in GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. TATORIS, TBTORIS: Timer Time-Out RIS status CAMRIS, CBMRIS: Timer Capture Mode Match RIS status CAERIS, CBERIS: Timer Capture Mode Event RIS status TAMRIS, TBMRIS: Timer Match RIS status RTCRIS: Real-Time-Clock RIS status Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spms376e.pdf, p748) MET2304 (FA24) 39 Interrupt Clear Register (GPTMICR) Type, Reset Value: W1C, 0x0000.0000 [Timer B] [Timer A] Register is used to clear the interrupt status bits in the GPTMRIS & GPTMMIS registers. Writing a ‘1’ to a bit clears the corresponding bit in the GPTMRIS & GPTMMIS registers. Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spms376e.pdf, p754) MET2304 (FA24) 40 GPTM Pre-scaler 16-bit Timers (non-concatenated): GPTMTnPR MET2304 (FA24) Periodic Timer Mode Pre-scaler NOT used when Timer is concatenated in both 16/32 or 32/64 bits Pre-scalar behaves differently in the various Timer modes. Timer configurations. Periodic / One-Shot Mode: When counting DOWN, the pre-scaler acts as a true pre-scaler. It contains the least-significant bits of the count. When counting UP, the pre-scaler acts as a timer extension & holds the most-significant bits (MSB) of the count. Input Edge Count & PWM Mode: Pre-scaler acts as a timer extension, regardless of the count direction. Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spms376e.pdf, p708) MET2304 (FA24) 42 Timer Pre-scaler in Periodic Mode Periodic Mode, Count DOWN: (TRUE PRE-SCALER) Pre-scaler forms the LSB bits; 8-bits width for 16-bit mode Timer. Pre-scaler counts down from ILR value to 0 before Timer counter counts down by 1. It behaves as if there are TWO Timers. 𝑆𝑦𝑠𝑡𝑒𝑚𝐶𝑙𝑜𝑐𝑘 Thus, timer counter counts down at frequency of ( ). 𝑃𝑟𝑒−𝑠𝑐𝑎𝑙𝑒𝑟 Timer count slows down! → this is what is meant by TRUE PRE- SCALER. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 TIMER CTR: TIMER Register (e.g. GPTMTAR) PRE-SCALER (8-bits) MET2304 (FA24) 43 Timer Pre-scaler in Periodic Mode Periodic Mode, Count UP: (TIMER EXTENSION) Pre-scaler forms the MSB bits. Pre-scaler acts as Timer-extension to 24 bits (16-bits + 8-bits). Timer is effectively a 24-bit Timer. It behaves a ONE concatenated 24-bit Timer. Timer counter counts at frequency of (𝑺𝒚𝒔𝒕𝒆𝒎𝑪𝒍𝒐𝒄𝒌). Bit: 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMER CTR: PRE-SCALER (8-bits) TIMER Register (e.g. GPTMTAR) [becomes a 24-bit Timer] Bit: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMER CTR: 24-bit Timer MET2304 (FA24) 44 Timer Pre-scale Register (GPTMTAPR, GPTMTBPR) Type, Reset Value: RW, 0x0000.0000 Register allows software TAPSR, TBPSR: GPTM Timer Prescale (8-bits) to extend the range of the timers when they are used individually. Timer count is extended through a Prescale TAPSRH, TBPSRH: GPTM Timer Prescale High Byte (8-bits) value. (not used in 16/32-bit timer modes) Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spmu376e.pdf, p760) MET2304 (FA24) 45 Pre-Scalar in Timer Operation In Periodic Count DOWN Mode, the Pre-scalar counts DOWN to 0 before the counter value is counted down. Ex 1: (16-bit Timer A) At 80MHz, if Pre-scalar (TAPR) = 0xFF, the counter value changes every (12.5 × 28) ns = counter resolution. 80MHz / 28 = 312,500 Hz = counter frequency with pre- scaler. At maximum Preload (TAILR) = 0xFFFF (16 bits), we get the largest possible count period/interval. 1 𝐶𝑜𝑢𝑛𝑡 𝐼𝑛𝑡𝑒𝑟𝑣𝑎𝑙 = × 65,536 = 209.7152𝑚𝑠 312,500 Periodic Mode: 216 = 65,536 When counting DOWN, pre-scaler acts as a true 0xFFFF = 65,535 pre-scaler. It contains the LSB bits of the count. MET2304 (FA24) 46 Pre-Scalar in Timer Operation Ex 2: In Ex 1, if Preload (TAILR) = 0xFFAA (65,450), the counter decrements at a time interval of: 𝐷𝑒𝑐𝑟𝑒𝑚𝑒𝑛𝑡 𝑖𝑛𝑡𝑒𝑟𝑣𝑎𝑙 = 65,451 × 12.5𝑛𝑠 × 256 = 209.44𝑚𝑠 ILR Clock Period PR MET2304 (FA24) 47 Pre-Scalar in Timer Operation In Periodic Count UP Mode, the Timer counter counts with the Pre-scalar value appended as its MSBs. Ex 3: At 80 MHz bus clock, if Pre-scalar (TAPR) = 0x3F and a Preload (TAILR) value of 0x55FF (16 bits), what is the time- out interval for the UP counter? At 80 MHz, period = 1/80 MHz = 12.5 ns When Timer is counting UP, the pre-scaler acts as a time extension => it becomes the MSB bits. Thus, counter load value = 0x3F.55FF (24 bits) = 4,150,783. 𝑇𝑖𝑚𝑒𝑜𝑢𝑡 𝐼𝑛𝑡𝑒𝑟𝑣𝑎𝑙 = (4,150,783 + 1) × 12.5𝑛𝑠 = 51.88𝑚𝑠 Periodic Mode: When counting UP, pre-scaler acts as Timer extension & holds the MSB bits of the count. MET2304 (FA24) 48 Timer Operation Example (130µs, 80MHz) Timer A If we want a Timer A Time-out interrupt Interrupts to happen at every 130µs: At 80MHz bus clock, period = 12.5ns. With a 16-bit count DOWN Timer, maximum count = 216 Time maximum interval = 216 x 12.5ns = 0.8192ms. Timer Interrupts at 130µs intervals Since 130µs < 0.8192ms, there is no need to make use of a pre-scaler. 130𝜇𝑠 No of counts = = 10,400 = 0𝑥28𝐴0 12.5𝑛𝑠 𝑅𝑒𝑙𝑜𝑎𝑑 𝑣𝑎𝑙𝑢𝑒 𝑻𝑨𝑰𝑳𝑹 = 0𝑥28𝐴0 − 1 = 0𝑥289𝐹 Pre-scaler (TAPR) = 0. MET2304 (FA24) 49 Timer Operation Example (1.8us, 80MHz) Timer A If we want a Timer A Time-out interrupt Interrupts to happen at every 1.80µs: At 80MHz bus clock, period = 12.5ns. With a 16-bit count DOWN Timer, maximum count = 216 Time maximum interval = 216 x 12.5ns = 0.8192ms. Timer Interrupts at 130µs intervals Since 1.80µs < 0.8192ms, there is no need to make use of a pre-scaler. 1.80𝜇𝑠 No of counts = = 144 = 0𝑥90 12.5𝑛𝑠 𝑅𝑒𝑙𝑜𝑎𝑑 𝑣𝑎𝑙𝑢𝑒 𝑻𝑨𝑰𝑳𝑹 = 0𝑥90 − 1 = 0𝑥8𝐹 Pre-scaler (TAPR) = 0. MET2304 (FA24) 50 Timer Operation Example (2.5us, 80MHz) Timer A If we want a Timer A Time-out interrupt Interrupts to happen at every 2.50µs: At 80MHz bus clock, period = 12.5ns. With a 16-bit count DOWN Timer, maximum count = 216 Time maximum interval = 216 x 12.5ns = 0.8192ms. Timer Interrupts at 130µs intervals Since 1.80µs < 0.8192ms, there is no need to make use of a pre-scaler. 2.50𝜇𝑠 No of counts = = 320 = 0𝑥140 12.5𝑛𝑠 𝑅𝑒𝑙𝑜𝑎𝑑 𝑣𝑎𝑙𝑢𝑒 𝑻𝑨𝑰𝑳𝑹 = 0𝑥140 − 1 = 0𝑥13𝐹 Pre-scaler (TAPR) = 0. MET2304 (FA24) 51 Timer Operation Example (5ms, 80MHz) Timer A If we want a Timer A Time-out Interrupts interrupt to happen at every 5ms: At 80MHz bus clock, period = 12.5ns. With a 16-bit count DOWN Timer, maximum count = 216 Time Timer Interrupts at 5ms maximum interval = 216 x 12.5ns intervals = 0.8192ms. Since 5ms > 0.8192ms, we need to make use of a pre-scaler. 5𝑚𝑠 We choose a pre-scaler division = 7. = 6.10 0.8192𝑚𝑠 Thus, TAPR = 7 – 1 = 6 5𝑚𝑠 Thus, Reload Value (TAILR) = = 57,143 = 0𝑥𝐷𝐹37 12.5𝑛𝑠 × 7 0xDF37 – 1 = 0xDF36 MET2304 (FA24) 52 Timer Match & Interrupt GPTMTnR, GPTMTnV, GPTMTnMATCHR, GPTMTnPMR MET2304 (FA24) Timer Register (GPTMTAR, GPTMTBR) Type, Reset Value: R0, 0xFFFF.FFFF Register shows current value of 16-bit Input Edge Count, Input Timer A counter in all cases Edge Time, PWM modes: (except for Input Edge Count & Bit (15:0) = counter value. Time modes). Bit (23:16) = prescaler (MSBs) 32-bit mode: behaves as a 32-bit Bit 31:24 = 0). register where upper 16-bits Input Edge Count: Register corresponds to GPTMTBR. contains number of edges that have 16-bit Periodic & One-shot modes: occurred. Bit (15:0) = counter value Input Edge Time: Register contains Bit (31:24) = 0 time at which the last edge event To read Pre-scaler – read bit took place. [23:16] of GPTMTAV register Source: Tiva TM4C123GH6PM Microcontroller Data Sheet MET2304 (FA24) 54 (spms376e.pdf, p764) Timer Value Register (GPTMTAV, GPTMTBV) Type, Reset Value: R/W, 0xFFFF.FFFF During READ, register shows 16-bit Periodic Down & One-shot current, free-running value of modes: Timer A in all modes. Bit 15:0 = counter value SW can use register value to Bit 23:16 = true pre-scaler Bit 31:24 = 0 determine time elapsed between an interrupt & ISR entry when 16-bit Periodic Up, Input Edge using the snapshot feature in Count & Time, PWM modes: Periodic mode. Bit 15:0 = counter value Bit 23:16 = pre-scaler (MSB) During WRITE, value written to Bit 31:24 = 0 register is loaded to GPTMTAR 32-bit Mode: register on the next clock cycle. Bit 31:16 = TBV register value Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spmu376e.pdf, p766) MET2304 (FA24) 55 Timer Match Register (GPTMTAMATCHR, GPTMTBMATCHR) Type, Reset Value: R/W, 0xFFFF.FFFF TAMR, TBMR = 32 bit Match value. In 16-bit mode, only bits 15:0 are used; the upper 16 bits are read as 0s. This register is loaded with a Match value. Interrupts can be generated when the Timer value is equal to the value in this register in one-shot or periodic mode. Interrupts enabled through the TAMIE, TBMIE (Match interrupt Enable) bit in Mode register. MET2304 (FA24) 56 Timer Pre-Scale Match Register (GPTMTAPMR, GPTMTBPMR) Type, Reset Value: R/W, 0x0000.0000 This register allows software to extend the range of the GPTMTAMATCHR, GPTMTBMATCHR when the timers are used individually. In 16-bit mode, TAPSMR, TBPSMR field contains the 8- bit pre-scaler value. MET2304 (FA24) 57 How a Timer Match Value Works … GPTMTnMATCHR & GPTMTAPMR Match Value in GPTM Timer A Match (GPTMTAMATCHR) & Pre-scale Match (GPTMTAPMR) register (optional, if used) can be used to compare with Current Value stored in the GPTM Timer A (GPTMTAV) register to trigger an interrupt or set a flag to indicate that a time value matching has occurred if both values are equal. When the contents of free-running Timer A counter & Timer A Match & Pre-scale Match registers are equal, the TAMRIS Flag goes up indicating there is a match. Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spmu376e.pdf, p758) MET2304 (FA24) 58 Periodic Timer Match Interrupt How do we enable Match interrupts for a Timer? Set the TnMIE (Match Interrupt Enable) bit of the Mode (TnMR) register. What scenario causes a Timer match interrupt to be generated? Match interrupt is generated when Timer value (TnV) equals the value loaded to the TnMATCHR (Timer Match) register & TnPMR (Prescale Match) register. Interrupt status bits are updated through the TnMIS (Mask Interrupt Status) & TnRIS (Raw Interrupt Status) register. MET2304 (FA24) 59 Periodic Timer Mode Initialization TM4C123GH6PM Tiva GPTM MET2304 (FA24) Periodic Timer Mode – Timer Registers Periodic Timer Mode is selected by TACMR = 0x02 in TAMR (Mode) register. Count UP or DOWN, selected by TACDIR bit. Timer Reload value is stored in TAILR register. Pre-scalar is stored in TAPR register. Timer is enabled or disabled through TAEN bit in CTL register. Timer can be used: Individually (Timer A or B) – 16 bit mode, or Concatenated (Timer (A + B)) – 32 bit mode. Source: Tiva TM4C123GH6PM Microcontroller Data Sheet (spmu376e.pdf, p708) MET2304 (FA24) 61 Periodic Timer Mode (16-bit) - Initialization 16-bit Timer Initialization: (assume Timer A) 1. Disabled Timer during start of initialization (TAEN = 0/CTL reg). 2. Configure Timer to 16-bit mode (CFG=0x04/CFG reg) 3. Set to Periodic mode (TAMR=0x02/TAMR reg) 4. Set Count Up/Down direction (DIR bit/TAMR reg) 5. Set initial count (TAILR reg). 6. Set Pre-scalar (TAPR reg). 7. Enable Time-out Interrupt (TATOIM = 1/IMR reg). 8. Clear Time-out Flag (write to TATOCINT bit/ICR reg) 9. Enable Timer (TAEN=1/CTL reg). MET2304 (FA24) 62 Ex: Periodic Timer Mode (16-bit) Initialization (Timer 0) #define PB_T0CCP0 6U // PB6 // other GPIO initialization codes GPIOB->AFSEL |= BIT(PB_T0CCP0); GPIOB->PCTL &= ~GPIO_PCTL_PB6_M; GPIOB->PCTL |= GPIO_PCTL_PB6_T0CCP0; SYSCTL->RCGCTIMER |= SYSCTL_RCGCTIMER_R0; while(0 == (SYSCTL->PRTIMER & SYSCTL_PRTIMER_R0)){}; // Timer 0 TIMER0->CTL &= ~TIMER_CTL_TAEN; TIMER0->CFG |= TIMER_CFG_16_BIT; TIMER0->TAMR |= TIMER_TAMR_TAMR_PERIOD ; TIMER0->TAMR &= ~TIMER_TAMR_TACDIR; TIMER0->TAILR = 0xF424; TIMER0->TAPR = 0xFF; TIMER0->IMR |= TIMER_IMR_TATOIM; TIMER0->ICR |= TIMER_ICR_TATOCINT; TIMER0->CTL |= TIMER_CTL_TAEN; MET2304 (FA24) 63 Periodic Timer Mode (32-bit) - Initialization 32-bit Timer Initialization: (assume Timer A) 1. Disabled Timer during start of initialization (TAEN = 0 /CTL reg). 2. Configure Timer to 32-bit mode (CFG=0x00/CFG reg) 3. Set to Periodic mode (TAMR=0x02/TAMR reg) 4. Set Count Up/Down direction (DIR bit/TAMR reg) 5. Set initial count (TAILR reg). 6. Set Pre-scalar to 0 (TAPR reg). 7. Enable Time-out Interrupt (TATOIM = 1/IMR reg). 8. Clear Time-out Flag (write to TATOCINT bit/ICR reg) 9. Enable Timer (TAEN=1/CTL reg). Note: In 32-bit mode, Timer A and Timer B are concatenated. In this mode, the Pre-scalar is NOT used. MET2304 (FA24) 64 Timer Interrupt Handlers (16/32-bit) Interrupt handlers names are pre-defined in file ‘startup_TM4C123.s’. DCD TIMER0A_Handler ; IRQ19: Timer 0A DCD TIMER0B_Handler ; IRQ20: Timer 0B DCD TIMER1A_Handler ; IRQ21: Timer 1A DCD TIMER1B_Handler ; IRQ22: Timer 1B DCD TIMER2A_Handler ; IRQ23: Timer 2A DCD TIMER2B_Handler ; IRQ24: Timer 2B DCD COMP0_Handler ; IRQ25: Analog Comparator 0............ DCD GPIOG_Handler ; IRQ31: GPIO Port G DCD GPIOH_Handler ; IRQ32: GPIO Port H DCD UART2_Handler ; IRQ33: UART2 Rx and Tx DCD SSI1_Handler ; IRQ34: SSI1 Rx and Tx DCD TIMER3A_Handler ; IRQ35: Timer 3A DCD TIMER3B_Handler ; IRQ36: Timer 3B DCD TIMER4A_Handler ; IRQ70: Timer 4A DCD TIMER4B_Handler ; IRQ71: Timer 4B............ DCD TIMER5A_Handler ; IRQ92: Timer 5A DCD TIMER5B_Handler ; IRQ93: Timer 5B MET2304 (FA24) 65 Timer Interrupt Handlers (32/64-bit) Interrupt handlers names are similarly defined for the wide Timers. DCD WTIMER0A_Handler ; IRQ94: Wide Timer 0A DCD WTIMER0B_Handler ; IRQ95: Wide Timer 0B DCD WTIMER1A_Handler ; IRQ96: Wide Timer 1A DCD WTIMER1B_Handler ; IRQ97: Wide Timer 1B DCD WTIMER2A_Handler ; IRQ98: Wide Timer 2A DCD WTIMER2B_Handler ; IRQ99: Wide Timer 2B DCD WTIMER3A_Handler ; IRQ100: Wide Timer 3A DCD WTIMER3B_Handler ; IRQ101: Wide Timer 3B DCD WTIMER4A_Handler ; IRQ102: Wide Timer 4A DCD WTIMER4B_Handler ; IRQ103: Wide Timer 4B DCD WTIMER5A_Handler ; IRQ104: Wide Timer 5A DCD WTIMER5B_Handler ; IRQ105: Wide Timer 5B MET2304 (FA24) 66 Timer Interrupt Handler Example of Timer 0A ISR: void TIMER0A_Handler( void ) { uint32_t status = TIMER0->RIS; // or MIS register TIMER0A_IRQHandler (status ); } extern void TIMER0A_IRQHandler( uint32_t Status ) { if( 0 != (Status & TIMER_RIS_TATORIS) ) { TIMER0->ICR |= TIMER_ICR_TATOCINT; } } MET2304 (FA24) 67 Enable Timer Interrupt void IRQ_Init( void ) { NVIC_EnableIRQ( TIMER0A_IRQn ); } MET2304 (FA24) 68 Defined Interrupt Sources in RIS Register #define TIMER_RIS_WUERIS 0x00010000 // GPTM Write Update Error Raw // Interrupt #define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt #define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt #define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event // Raw Interrupt #define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match // Raw Interrupt #define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw // Interrupt (Defined in file ‘TM4C123GH6PM7.h’.) MET2304 (FA24) 69 SysTick Timer vs General-Purpose Timers SysTick Timer is part of the ARM-Core definition. Almost all ARM Cortex-M processors have a SysTick timer. Because SysTick is part of the ARM Core, it is usually used by the OS for task scheduling. General-Purpose Timers (or just Timers) are implemented as part of a microcontroller’s peripherals. It is specific to the microcontroller and not part of the ARM core. SysTick Timer is usually simpler in design and therefore easier to program. General-Purpose Timers are usually more flexible and have I/O pins to interface externally. Also, SysTick Timer is special in the sense that we do not have to clear interrupts within the Systick_handler()! MET2304 (FA24) 70  Please email me at [email protected] if you find any typos or errors in the lecture notes. MET2304 (FA24) 71