MET2304 GPTM Timer Modules and Registers

GPTM Timer Modules

• The TM4C123G microcontroller has six General Purpose Timer Modules (GPTM).
• There are six 16/32-bit GPTMs and six 32/64-bit GPTMs.
• In MET2304 we focus on the 16/32-bit GPTMs, namely Timer 0 to 5.
• Each 16/32-bit GPTM contains two 16-bit timers: Timer A and Timer B.
• They operate independently as separate timers or can work together as one 32-bit timer.

GPTM Timer Registers

• Each GPTM module has a set of control and status registers, some of which have A and B variants.
• Timer registers can be grouped by:
  • Timer Control/Configuration
  • Timer Count Status
  • Timer Interrupt Control/Status
• Key configuration registers: GPTMCFG, GPTMCTL, GPTMTAMR, GPTMTBMR, GPTMTAILR, GPTMTBILR, GPTMTAMATCHR, GPTMTBMATCHR, GPTMTAPR, GPTMTBPR
• Key status registers: GPTMTAR, GPTMTBR, GPTMTAV, GPTMTBV, GPTMTAPV, GPTMTBPV
• Key interrupt registers: GPTMIMR, GPTMMIS, GPTMICR

Timer Data Structure

• Each GPTM module has a corresponding data structure defined in the TM4C123GH6PM7.h file.
• These data structures provide access to the registers using a specific naming convention for each timer module (e.g. TIMER0, TIMER1, etc.)

Timer Configuration Registers

• GPTMCFG: Configures the global operation of the GPTM module, including:
  • TACDIR & TBCDIR: Determine the count direction (up or down).
  • TAMR & TBMR: Set the timer mode (e.g. capture mode, periodic mode).
• GPTMCTL: Controls the timer module, including:
  • GPTMCTL.TAEN & GPTMCTL.TBEN: Enable Timer A and Timer B respectively.
• GPTMTnMR: (Tn = A or B) defines the timer operation mode and direction:
  • TnMR [1:0]: 0x2 for periodic timer mode.
  • TnCDIR: 1 for count-up, 0 for count-down.

Timer Interval Load Register

• GPTMTAILR & GPTMTBILR: Load the starting countdown value or upper bound for the timeout event depending on count direction.
• In 16-bit mode, GPTMAILR is a 16-bit register, while in 32-bit mode, GPTMTAILR and GPTMTBILR work together as a 32-bit register.

GPTM Periodic Mode

• To configure a GPTM timer in periodic mode:
  • Clear the 2 least significant bits of the TnMR register.
  • Set the Mode bits (TnMR[1:0]) to 0x2.
• Counting direction is defined by TnCDIR bit.
• GPTMTAILR & GPTMTBILR register values determine count interval/period.
• The timer counts up or down at the system clock frequency.

GPTM Pre-scaler

• Pre-scaler extends the count range, especially in periodic and one-shot modes.
• In periodic mode, the pre-scaler acts as a true pre-scaler in count-down mode, forming the LSB bits.
• In count-up mode, the pre-scaler acts as a timer extension holding the MSB bits.
• The pre-scaler is not used in concatenated timer modes (16/32 or 32/64 bits).

Timer Pre-scaler in Periodic Mode

• Count DOWN: The pre-scaler counts down from the ILR value to 0 before the timer counts down by 1, effectively slowing down the timer count frequency (True Pre-scaler).
• Count UP: The pre-scaler forms the MSB bits, extending the timer counter to 24 bits. The timer operates as a single, concatenated 24-bit counter.

Timer Pre-scale Register

• GPTMTAPR & GPTMTBPR: Extend the timer count range, particularly for non-concatenated 16-bit timers.
• GPTMTAPS & GPTMTBPS: Provide a snapshot of the current prescaler value, enabling real-time observation of prescaler behavior.

Pre-Scalar in Timer Operation

• In periodic count-down mode, the pre-scaler acts as a true pre-scaler, slowing down the counter frequency.
• The timer resolution and count interval are directly affected by the pre-scaler value.
• The maximum preload value (TAILR or TBILR) determines the largest achievable count period/interval.