DLD Assignment 2 PDF

## Assignment Answer Booklet **Hall Ticket No:** 23k81A04L6 **Name of the Student:** kethan Kumar **Course:** B.TECH **Branch:** ECE **Year:** I/II/III/IV **Sem:** II **Assignment:** I/II **Subject Name:** DLD **Last Date of Submission:** **Actual Date of Submission:** **Signature of the Studen...

## Assignment Answer Booklet **Hall Ticket No:** 23k81A04L6 **Name of the Student:** kethan Kumar **Course:** B.TECH **Branch:** ECE **Year:** I/II/III/IV **Sem:** II **Assignment:** I/II **Subject Name:** DLD **Last Date of Submission:** **Actual Date of Submission:** **Signature of the Student:** **Signature of the Evaluator:** ### Marks Awarded | Q.No. | a | b | Total | |---|---|---|---| | 1 | | | | | 2 | | | | | 3 | | | | | 4 | | | | | 5 | | | | | **Total** | | | | ### Start writing from here ### 1. Explain Master slave flip-flop The Master slave JK- flip flop is designed using docked SR-Flip flop. The clock signal is connected directly to the master flip-flop but is connected through inverter. **Clock signal:** * When the clock is high, the master captures the JK inputs while the slave remains inactive. * When the clock is low, the slave transfers the master’s output, preventing the race-around condition. **Master slave J-K flip-flop using NAND gates:** #### Case 1: When J = 1 and k = 0 & clock is high * Master will be set making S high and R low. * When the clock becomes low, the slave will be set making Q high * When the clock is low. the slave transfers the master’s output, preventing the race-around condition. #### Case 2: When J = 0 & K = 1, * The master reacts on the positive clock, making S low and R high. * When the clock goes low, the slave is reset, making Q low, and Q high. #### Case 3: When J = 1, K = 1 The master and slave toggle states on each clock cycle, causing the flip-flop to toggle #### Case 4: When both J and K input are low, there will b no change in the output state of the flip-flop. ### 2. Explain Universal shift Register: Universal shift register is a register that can perform each and every function of shift register i.e SISO, SIPO, PIPO, PISO **2. Explain Universal shift Register:** Universal shift register is that register which can perform each and every function of shift register i.e SISO, SIPO, PIPO, PISO **Universal shift Register:** Universal shift register is that register which can perform each and every function of shift register ie SISO, SIPO, PIPO, PISO **Diagram:** * **DSR:** Right shift input * **DSL:** Left shift input * **ABCD:** Parallel data input **Case 1: S1 = 0 & S0 = 0** The decoder output 00 is high enabling AND gates 13, 14, 15 & 16, which connect QA, QB, QC and QD to FF1, FF2, FF3 & FF4 inputs. Therefore, the shift register data remains unchanged. **Case 2: S1 = 0 & S0 = 1** The decoder output 01 is high enabling AND gates 9, 10, 11 & 12. Under this condition the input to flip-flop FF1, FF2, FF3, and FF4 are QA, QC, QD, and QSL **Case 3: S1 = 1 & S0 = 0** The decoder output 02 is high, enabling AND gates 5, 6, 7 and 8. Under this condition flip-flops FF1, FF2, FF3, and FF4 receive inputs A, B, C and D allowing parallel data loading from the A, B, C, D input lines **Case 4: S1 = 1 & S0 = 1** When decoder output 03 is high, And gates 1,2,3, & 4 are enabled and flip-flops FF1, FF2, FF3, and FF4 receive inputs DSR, QA, QB, and QC causing register data to shift right. ### 3. Illustrate capabilities and limitations of FSM #### Capabilities * **Equivalence and Minimization:** In a state diagram or table, some states may be redundant, meaning they can be reached through other states Minimizing the number of states reduces the required memory elements in a sequential machine. States a1 and 02 are equivalent if, for any input sequence, they input sequence they identical outputs. * **Machine equivalence:** Machine Xa and Xb are equivalent if for every state of Xa, there is a corresponding equivalent state in Xb and vice versa * **K-Equivalence:** Two states a1 and a2 in a machine X are said. to be K-equivalent if a1 and a2, when excited by an input sequences of K-symbol yield identical output sequence. The groups states into equivalent classes enabling the reduction of redundant states and Simplifying the FSM without changing it behavior. #### Limitations **No infinite sequences:** FSM's cannot process infinite sequence because they have a finite number of states and can't store infinite information. **Limited Memory:** The FSM’s limited memory restricts its ability to handle operations like multiplying arbitrarily large binary numbers, as it cannot store large partial product. **No Parallel Processing:** FSM process one state at a time, which limits their performance in parallel computation scenarios. If the output is not periodic then no finite state machine can produce the sequence. **Inflexibility:** Any change in system behaviour requires redefining the state diagram", which can be complex and time consuming, especially for dynamic or adaptive systems. ### 4. Write about various blocks of ASM charts. The main segment of ASM are * **State box:** The state in control sequence, is indicated by state-box i.e Rectangle. It may contain an output list, and a state code may be placed outside the box at top. The state name is placed left side of the box. * **Decision box:** A decision box, represented by a diamond-shaped symbol, evaluates a Boolean condition to determine the control flow. It has two branches (T/0 or True/False) based on the input conditions, and the control flow to one of the branches is assigned. * **Conditional box:** A list of conditional outputs. The conditional Box, with an oval shape and curved ends, specifies outputs that depend on both system state and input. It receives its input path from an exit branch of the decision box.