CF_unit1.pdf

VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Digital Systems & Architecture Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Combinational Circuit A combinational circuit is a connected arrangement of logic gates with a set of inputs and outputs. – encoder, decoder, multiplexer and demultiplexer The outputs of Combinational Logic Circuits are only determined by the logical function of their current input state, logic “0” or logic “1”, at any given instant in time. In other words, in a Combinational Logic Circuit, the output is dependant at all times on the combination of its inputs. Thus a combinational circuit is memoryless. Combinational Logic Circuits are made up from basic logic NAND, NOR or NOT gates that are “combined” or connected together to produce more complicated switching circuits. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO Combinational Logic Circuits are made up from basic logic NAND, NOR or NOT gates that are “combined” or connected together to produce more complicated switching circuits. Some of the characteristics of combinational circuits are following − The output of combinational circuit at any instant of time, depends only on the levels present at input terminals. The combinational circuit do not use any memory. The previous state of input does not have any effect on the present state of the circuit. A combinational circuit can have an n number of inputs and m number of outputs. VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce A combinational circuit is a connected arrangement of logic gates with a set of inputs and outputs. – encoder, decoder, multiplexer and demultiplexer The outputs of Combinational Logic Circuits are only determined by the logical function of their current input state, logic “0” or logic “1”, at any given instant in time. In other words, in a Combinational Logic Circuit, the output is dependant at all times on the combination of its inputs. Thus a combinational circuit is memoryless. Combinational Logic Circuits are made up from basic logic NAND, NOR or NOT gates that are “combined” or connected together to produce more complicated switching circuits. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Half - Adder A Half-adder circuit needs two binary inputs and two binary outputs. The input variable shows the augend and addend bits whereas the output variable produces the sum and carry. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti…. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti…. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Full Adder Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit numbers A and B, and carry c. The full adder is a three input and two output combinational circuit. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti… Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti… Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Multiplexer A multiplexer is a combinational circuit that has 2n input lines and a single output line. Simply, the multiplexer is a multi-input and single-output combinational circuit. The binary information is received from the input lines and directed to the output line. On the basis of the values of the selection lines, one of these data inputs will be connected to the output. Unlike encoder and decoder, there are n selection lines and 2n input lines. So, there is a total of 2N possible combinations of inputs. A multiplexer is also treated as Mux. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Multiplexers, or MUX’s, can be either digital circuits made from high speed logic gates used to switch digital or binary data or they can be analogue types using transistors. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce 4x1 Multiplexer 4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y. The block diagram of 4x1 Multiplexer is shown in the following figure. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Demultiplexer A demultiplexer (also known as a demux or data distributor) is defined as a circuit that can distribute or deliver multiple outputs from a single input. A demultiplexer can perform as a single input with many output switches. The demultiplexer’s output lines are ‘n’ in number, the select line number is ‘m’ and n = 2m. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... The demux can also perform as a binary to decimal decoder. The data input line should be at the logic 1 level, and the binary input is given to the select input lines. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Input 1 input bit is present. Here it is Data D. Outputs The number of outputs is four. They are Y0, Y1, Y2, and Y3. Control Bits Two control bits are used here. They are A and B. The input data bit is sent to the data bit of the output lines depending on the select input or control bit’s value. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Sequential Circuits The combinational circuit does not use any memory. Hence the previous state of input does not have any effect on the present state of the circuit. But sequential circuit has memory so output can vary based on input. This type of circuits uses previous input, output, clock and a memory element. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... The sequential circuit is a special type of circuit that has a series of inputs and outputs. The outputs of the sequential circuits depend on both the combination of present inputs and previous outputs. The previous output is treated as the present state. So, the sequential circuit contains the combinational circuit and its memory storage elements. A sequential circuit doesn't need to always contain a combinational circuit. So, the sequential circuit can contain only the memory element. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce K-Map (Karnaugh Map) In many digital circuits and practical problems we need to find expression with minimum variables. We can minimize Boolean expressions of 3, 4 variables very easily using K-map without using any Boolean algebra theorems. K-map can take two forms Sum of Product (SOP) and Product of Sum (POS) according to the need of problem. K-map is table like representation but it gives more information than TRUTH TABLE. We fill grid of K-map with 0’s and 1’s then solve it by making groups. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Steps to solve expression using K-map- Select K-map according to the number of variables. Identify minterms or maxterms as given in problem. For SOP put 1’s in blocks of K-map respective to the minterms (0’s elsewhere). For POS put 0’s in blocks of K-map respective to the maxterms(1’s elsewhere). Make rectangular groups containing total terms in power of two like 2,4,8..(except 1) and try to cover as many elements as you can in one group. From the groups made in step 5 find the product terms and sum them up for SOP form. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce SOP FORM K-map of 3 variables- – Z= ∑A,B,C(1,3,6,7) From red group we get product term— A’C From green group we get product term— AB Summing these product terms we get- Final expression (A’C+AB) Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce K-map for 4 variables F(P,Q,R,S)=∑ (0,2,5,7,8,10,13,15) From red group we get product term— QS From green group we get product term— Q’S’ Summing these product terms we get- Final expression (QS+Q’S’) Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce POS FORM K-map of 3 variables- F(A,B,C)=π(0,3,6,7) From red group we find terms A B C’ Taking complement of these two A’ B’ C Now sum up them (A’ + B’ + C) From green group we find terms B C Taking complement of these two terms B’ C’ Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Now sum up them (B’+C’) From brown group we find terms A’ B’ C’ Taking complement of these two ABC Now sum up them (A + B + C) We will take product of these three terms :Final expression (A’ + B’ + C) (B’ + C’) (A + B + C) Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Comparison of Computer Organization & Architecture, Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Computer Components and Functions Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Input Unit :The input unit consists of input devices that are attached to the computer. These devices take input and convert it into binary language that the computer understands. Some of the common input devices are keyboard, mouse, joystick, scanner etc. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Central Processing Unit (CPU) : Once the information is entered into the computer by the input device, the processor processes it. The CPU is called the brain of the computer because it is the control center of the computer. It first fetches instructions from memory and then interprets them so as to know what is to be done. If required, data is fetched from memory or input device. Thereafter CPU executes or performs the required computation and then either stores the output or displays on the output device. The CPU has three main components which are responsible for different functions – Arithmetic Logic Unit (ALU), Control Unit (CU) and Memory registers Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Arithmetic and Logic Unit (ALU) :The ALU, as its name suggests performs mathematical calculations and takes logical decisions. Arithmetic calculations include addition, subtraction, multiplication and division. Logical decisions involve comparison of two data items to see which one is larger or smaller or equal. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Control Unit : The Control unit coordinates and controls the data flow in and out of CPU and also controls all the operations of ALU, memory registers and also input/output units. It is also responsible for carrying out all the instructions stored in the program. It decodes the fetched instruction, interprets it and sends control signals to input/output devices until the required operation is done properly by ALU and memory. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Memory Registers : A register is a temporary unit of memory in the CPU. These are used to store the data which is directly used by the processor. Registers can be of different sizes(16 bit, 32 bit, 64 bit and so on) and each register inside the CPU has a specific function like storing data, storing an instruction, storing address of a location in memory etc. The user registers can be used by an assembly language programmer for storing operands, intermediate results etc. Accumulator (ACC) is the main register in the ALU and contains one of the operands of an operation to be performed in the ALU. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Memory : Memory attached to the CPU is used for storage of data and instructions and is called internal memory The internal memory is divided into many storage locations, each of which can store data or instructions. Each memory location is of the same size and has an address. With the help of the address, the computer can read any memory location easily without having to search the entire memory. when a program is executed, it’s data is copied to the internal memory ans is stored in the memory till the end of the execution. The internal memory is also called the Primary memory or Main memory. This memory is also called as RAM, i.e. Random Access Memory. The time of access of data is independent of its location in memory, therefore this memory is also called Random Access memory (RAM). Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Output Unit : The output unit consists of output devices that are attached with the computer. It converts the binary data coming from CPU to human understandable form. The common output devices are monitor, printer, plotter etc. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Interconnection structures : The processors must be able to share a set of main memory modules & I/O devices in a multiprocessor system. This sharing capability can be provided through interconnection structures. The interconnection structure that are commonly used can be given as follows – Time-shared / Common Bus Cross bar Switch Multiport Memory Multistage Switching Network (Covered in 2nd part) Hypercube System Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Time-shared / Common Bus In a multiprocessor system, the time shar0ed bus interconnection provides a common communication path connecting all the functional units like processor, I/O processor, memory unit etc. The figure below shows the multiple processors with common communication path (single bus). Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... To communicate with any functional unit, processor needs the bus to transfer the data. To do so, the processor first need to see that whether the bus is available / not by checking the status of the bus. If the bus is used by some other functional unit, the status is busy, else free. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... A processor can use bus only when the bus is free. The sender processor puts the address of the destination on the bus & the destination unit identifies it. In order to communicate with any functional unit, a command is issued to tell that unit, what work is to be done. The other processors at that time will be either busy in internal operations or will sit free, waiting to get bus. We can use a bus controller to resolve conflicts, if any. (Bus controller can set priority of different functional units) This Single-Bus Multiprocessor Organization is easiest to reconfigure & is simple. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... This interconnection structure contains only passive elements. The bus interfaces of sender & receiver units controls the transfer operation here. To decide the access to common bus without conflicts, methods such as static & fixed priorities, First-In-Out (FIFO) queues & daisy chains can be used. Advantages – Inexpensive as no extra hardware is required such as switch. Simple & easy to configure as the functional units are directly connected to the bus. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Disadvantages – Major fight with this kind of configuration is that if malfunctioning occurs in any of the bus interface circuits, complete system will fail. Decreased throughput — At a time, only one processor can communicate with any other functional unit. Increased arbitration logic — As the number of processors & memory unit increases, the bus contention problem increases. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Multiple bi-directional buses : Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Apart from the organization, there are many factors affecting the performance of bus. They are – Number of active devices on the bus. Data width Error Detection method Synchronization of data transfer etc. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Advantages of Multiple bi-directional buses – Lowest cost for hardware as no extra device is needed such as switch. Modifying the hardware system configuration is easy. Less complex when compared to other interconnection schemes as there are only 2 buses & all the components are connected via that buses. Disadvantages of Multiple bi-directional buses – System Expansion will degrade the performance because as the number of functional unit increases, more communication is required but at a time only 1 transfer can happen via 1 bus. Overall system capacity limits the transfer rate & If bus fails, whole system will fail. Suitable for small systems only. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Crossbar Switch : A point is reached at which there is a separate path available for each memory module, if the number of buses in common bus system is increased. Crossbar Switch (for multiprocessors) provides separate path fro each module. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Multiport Memory : In Multiport Memory system, the control, switching & priority arbitration logic are distributed throughout the crossbar switch matrix which is distributed at the interfaces to the memory modules. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Hypercube Interconnection : This is a binary n-cube architecture. Here we can connect 2n processors and each of the processor here forms a node of the cube. A node can be memory module, I/O interface also, not necessarily processor. The processor at a node has communication path that is direct goes to n other nodes (total 2n nodes). There are total 2n distinct n-bit binary addresses. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce BUS Interconnection Computer consists of a CPU, Main Memory and I/O Unit. For data to flow between these components we need some kind of interconnections. hese components are interconnected by using a set of parallel lines (Conducted Wires). Each of these lines can be used to transfer a sequence of bits from one component of the computer to the other component. This is a set of parallel lines is called BUS. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Generally a computer has more than one bus interconnection. The bus used to connect the main components of a computer is called the System Bus. General-purpose computers have a 70-100 line system bus. The system bus is divided into three main categories. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Control Bus: These lines are use to transmit different commands from one component to the other. For example, if the CPU wants to read data from the main memory; it will send the memory read command to the main memory of the computer. The control bus is also used to transmit other control signals like ACKS (Acknowledgement Signals).For example when CPU give a command to the main memory for writing data, the memory sends a acknowledgement signal to the CPU after writing the data successfully so that the CPU can move forward and perform some more actions. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Data Bus: On the system bus 32 or 64 lines are reserved to transfer data from one component to the other. These lines are commonly known as the data bus. A 64-line data bus can transfer 64 bits of data simultaneously so it is not difficult to see that the width of the data bus has a direct impact on the performance of the computer. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Address Bus: As we know that many components are connected to one another through the system bus so it is important to assign a unique ID to each component. This ID is called the address of that component. When a computer component wants to communicate with another, it uses a few of the system bus lines to specify the destination component by using its address. These lines are commonly known as the address bus. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Programmed I/O Programmed I/O is one of the three techniques we use for I/O transfer. The other two methods for the same are interrupted I/O and (direct memory access) DMA. Programmed I/O is a technique or approach that we use to transfer data between the processor and the I/O module. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Functioning of programmed I/O The processor is executing a program and encounters an instruction relating to I/O operation. The processor then executes that instruction by issuing a command to the appropriate I/O module. The I/O module will perform the requested action based on the I/O command issued by the processor (READ/WRITE) and set the appropriate bits in the I/O status register. The processor will periodically check the status of the I/O module until it find that the operation is complete. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce I/O Commands Whenever the processor experience the I/O related instruction, to execute this I/O instruction the processor issues two things I/O command and address on the bus which is decoded by every I/O module connected to the system. Whichever I/O module is addressed by the processor recognizes this address respond to the issued I/O command. The processor issue the I/O commands to the I/O module can be of four types. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Control: This I/O command activates the I/O module addressed by the processor and directs it to the task it has to perform. This command can be customized depending upon the type of peripherals. Test: This I/O command tests the status of the I/O module and its peripherals to ensure that the addressed peripheral is powered on and available for the task. This command also tests whether the most recent I/O operation has completed successfully or if any error has occurred. Read: This I/O command lets the I/O module extract the data from the corresponding peripheral and store it in its internal buffer. Further, the I/O module can place this data over the data bus on the processor’s demand. Write: This I/O command lets the I/O module accept the data over the data bus and transmit it to the corresponding peripheral. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce I/O Instructions The I/O instruction encountered by the processor is issued to the processor by the main memory. And to execute this I/O instruction the processor provides the I/O command to the corresponding I/O device. Thereby the I/O instruction cab is simply mapped onto the I/O command. Usually, there is a simple one-to-one relationship between I/O instruction and I/O command. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Interrupt Driven I/O Interrupt driven I/O is an approach to transfer data between ‘memory’ and ‘I/O devices’ through the ‘processor’. The other two techniques for the same are programmed I/O and direct memory access (DMA). The interrupt-driven I/O involves the use of interrupt to exchange data between I/O and memory. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Functioning of Interrupt Driven I/O Consider that the data has to be stored in the main memory from the I/O module as input from the I/O module’s point of view. 1. For this, the processor issues a READ I/O command to the corresponding I/O module and proceeds with some other useful tasks. It does not wait for the I/O module to get ready with the desired data. 2. The I/O module then processes this READ I/O command and reads the data from the addressed peripheral device. The I/O module stores the read data into its data register and issues an interrupt signal to the processor over the control line in the system bus. 3. When the processor requests the data from the I/O, it places the data over the data line of the system bus. Once the I/O module transfers the data to the processor it set itself ready for another I/O transfer. Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO VIVEKANAND EDUCATION SOCIETY’S College of Arts, Science and Commerce Conti.... Name of the Teacher: Laxmi Tiwari Class:FYB.Sc CS Subject :CO

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