Computer Architecture PDF

Basic Computer Structure ▪ RAM (Random Access Memory) is a memory that can be written or read. It is used to keep data during the microprocessor process the program. ▪ PIO (Peripheral Input Output) is the port for interfacing with the external peripheral devices....

Basic Computer Structure ▪ RAM (Random Access Memory) is a memory that can be written or read. It is used to keep data during the microprocessor process the program. ▪ PIO (Peripheral Input Output) is the port for interfacing with the external peripheral devices. Data bus OSC clk Port A Micro ROM RAM PIO Port B processor Address bus rst_n Control bus vdd gnd vdd  Computer Structure Computer Data bus OSC clk Port A It read instruction (fetch( Micro ROM RAM PIO Port B processor end Excute instruction Address bus rst_n Control bus VDD GND VDD  Basic Processor Architecture - could Rx Ry Data bus Ro Ri. ,... + Ro... Rig defined ARM > - 10 Data Registers is used to store data for R R calculation. CPU can read Program E E these registers faster than Counter G …… G data memory, so some (PC) FLAG processor has many data 0 N Z C registers such as 8 to 64 to C T I N reduce the data memory R R V ALU L access. Data Registers Address bus Control Bus Ro , RisRzy--- - Roy - by Registers  Data Registers ▪ Data Registers are the registers that stores the read data from and written data to the RAM. ▪ CPU computes arithmetic and logic operations from Data Registers. ▪ Data Registers act as buffers, allowing the processor and memory units (RAM) to act independently. CPU - Data RAM ALU Reg X = Ram and All. no relation between ARM Processor Data Register ARM processor has 16 Data registers R0-R15. They can be split into 3 groups. These group differ in the way they are banked and in their special-purpose uses 1. General-purpose register : R0 to R12 > - variable Each of them refers to the same 32-bit physical register in all processor modes. They are completely general-purpose registers, with no special uses implied by the architecture. Ru-Rio Riz = R7 = RotRa R1 = R28Rs ARM Processor Data Register 2. Special Register R13-R15 call ▪ R13 is a stack pointer called as SP. > - function ▪ R14 is a link register called as LR. later ▪ R15 (Program Counter) from RAM Address so I Read data I 2 S if a want reset program , change 0.  Basic Processor Architecture Data bus instruction RIS Program Counter (PC) R R is used Program to keep Counter (PC) the address of Program E E Iscurrent instruction. used to keep Normally, it the address of current Counter G …… G starts at instruction. 0 and Normally, it startsincrease one at 0 and increase (PC) FLAG - byby one one one to readtothe read the If next next instruction. there 0 N Z C isinstruction. C If there a branch instruction, is ato branch it will jump that RO R1Y T I N R R instruction, address instead. it will jump to that V ALU L address instead. Data Registers Address bus Rom Control Bus Program Counter ▪ A program counter is a register in a computer processor that contains the address (location) of the instruction being executed at the current time. As each instruction gets fetched, the program counter increases its stored value by 1. After each instruction is fetched, the program counter points to the next instruction in the sequence. When the computer restarts or is reset, the program counter normally reverts to 0. Rom Program bus Program Instruction Memory Register Address bus Program (IR) (Program Code) Counter & (PC) Sn Program Counter Pl = Ro = a # Python // Pseudo Assembly 00 : R0 = 1 01 : R1 = 0 a=1 02 : if (R1==10) Z=1 else Z=0 for x in range(0,10) : 03 : if (Z==1) Jump to 07 a=a+a 04 : R1 = R1+1 / 05 : R0 = R0+R0 & == x=0 RI = 10) - 06 : Jump to 02 ( Y 07 : R1 = 0; not B 2 = 0  Basic Processor Architecture calculation unit Data bus ALU (Arithmetic Logic R R RO RI Unit) Program E E is used to calculate Counter G …… G ↓ ↓ (PC) FLAG arithmetic function such Z 0 N C as add, subtract, multiply, C T I divide and logic such as N R R and, or, not. V ALU L Data Registers Address bus R2L Control Bus Ro + P Re =  Arithmetic Logic Unit (ALU) logic/AND/OR 1... Arithmetic Logic Unit (ALU) is a digital circuit that performs arithmetic and bitwise operations on integer binary number. This contrasts with a floating-point unit (FPU), which operates on floating point numbers. It is a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs). R2 R3 - l ↓ A8B I B AtB & & ↑ + =& R2+ Rz nat ADD ou I suB = Ry = R2+ Rs ALU Operation Roll 000 Re = RofRi = dolo ▪ Arithmetic operations ▪ Bitwise operations - Addition : R2 = R0+R1 - AND : R2 = R0 & R1 - Subtraction : R2 = R0-R1 - ORR : R2 = R0 | R1 - Multiplication : R2 = R0*R1 - EOR : R2 = R0 ^ R1 flip T - 2’s Complement : R2 = ~R0+1 - INV : R2 = ~R0 - Increment : R2 = R1+1 - Decrement : R2 = R1-1 ALU Operation ▪ Bit Shift operations Arithmetic ArithmeticShift RightRight Shift - Arithmetic Shift Right - Logical Shift Left / Right - Rotate Left / Right Logical Shift Right Logical Shift Left Arithmetic Shift Right Arithmetic Shift Left  Basic Processor Architecture Data bus 4 flags ECNY FLAG R R Keep the status from data Program E E processing. Counter G …… G (PC) FLAG 0 Z N C C T I N R R V ALU L Data Registers Address bus Control Bus Processor FLAGS register ▪ The FLAGS register is the status register that contains the current state of a CPU. The size and meanings of the flag bits are architecture dependent. It usually reflects the result of arithmetic operations as well as information about restrictions placed on the CPU operation at the current time. ▪ ARM processor has 4-bit flags. Usually, it is used for condition decision, branch jump etc. ARM processor FLAG registers ▪ N bit (Negative) : is set if the result of operation in negative (MSB=1) (Assume the operation is signed) R0 = 0x30; // 48 24 =- 48 - R1 = 0x40; // 64 R2 = R0-R1; // After execute R2 = 0xF0, N-bit = 1 R0 = 0x33; // 51 io 1011 of 7 signed R1 = 0x30; // 48 R2 = R0-R1; // After execute R2 = 0x03, N-bit = 0 & 100 101 ARM processor FLAG registers ▪ Z bit (Zero) : is set if the result of operation in zero (all bit is zero) R0 = 0x30; // 48 = R1 = 0x30; // 48 u8r48 R2 = R0-R1; // After execute R2 = 0x00, Z-bit = 1 R0 = 0x33; // 51 48 : 3 31. R1 = 0x30; // 48 R2 = R0-R1; // After execute R2 = 0x03, Z-bit = 0 ARM processor FLAG registers ▪ C bit (Carry) : is set if the result of produced a carry (Assume that the operation is unsigned) o I 10 2011 R0 = 0x01; // 1. 1 000100lf R1 = 0xFF; // 255 R2 = R0+R1; // After execute R2 = 0x00, C-bit = 1 R3 = 0x01; // 1 250 = 100000000 R4 = 0x01; // 1 R5 = R3+R4; // After execute R5 = 0x02 // C-bit = 0 ARM processor FLAG registers ▪ V bit (Overflow) : is set if the result produced an overflow. (Assume the operation is signed) R0 = 0x81; // -127 - 18 (-127 + -127 Should be -254) < 128 127 - R1 = 0x81; // -127 overflow R2 = R0+R1; // After execute R2 = 0x02, V-bit = 1 R0 = 0x01; // 1 R1 = 0xFF; // -1 R2 = R0+R1; // After execute R2 = 0x00, V-bit = 0 Flag Summary ▪ C-Flag is set when there is a carry out. ▪ N-Flag is set when MSB is 1. ▪ Z-Flag is set when result is 0. ▪ V-Flag is set when P+P = N or N+N = P.  Basic Processor Architecture Data bus instruction Control Box (CTRL) is used to control the function R2 of CPU R R RO Ri Program E E Counter G …… G FLAG Instruction Register (IR) (PC) 0 Z is used to store the current N C C t T I instruction and read by the N R R control box to manage the V ALU L function of CPU Data Registers Address bus o fo Rom Control Bus Address Control Box ▪ Control box interpret the instruction code (such as ADD, SUB, MUL) and control the data flow of the CPU. For example, it will select the adder output to the output register when the command is ADD. ROR Ro + = Rc v ALU ADD ADD MUL ****** AND CTRL IR & & I 10 Rotte ROAR Ri RoSR Met Type of Computer Architecture There are 2 main computer architecture. ▪ Harvard Architecture ▪ Von Neumann Architecture Von Neumann Architecture (1945) ▪ Named after John Von Neumann Princeton, he designed a computer architecture whereby data and instructions would be retrieved from memory, operated on by an ALU, and moved back to memory (or I/O) ▪ Hardware consists of 3 units RAhn CPU (control unit, ALU, registers) Memory (stores programs and data) I/O System (including secondary storage) Rom ▪ Instructions in memory are executed sequentially unless a program instruction explicitly changes the order. Von Neumann Architecture Man Romn ▪ There is a single pathway used to move both data and instructions between memory, I/O and CPU ▪ the pathway is implemented as a bus ▪ the single pathway creates a bottleneck ▪ known as the von Neumann bottleneck ▪ A variation of this architecture is the Harvard architecture which separates data and instructions into two pathways ▪ Another variation, used in most computers, is the system bus version in which there are different buses between CPU and memory and memory and I/O Name of first CPU-Harvard Harvard Architecture ▪ Harvard architecture is a type of computer architecture that separates its memory into two parts, so data and instructions are stored separately. The architecture also has separate buses for data transfers and instruction fetches. This allows the CPU to fetch data and instructions at the same time. Harvard Architecture The key features….. 1. The two different memories can have different characteristics: for example, in embedded systems, instructions may be held in read-only memory while data may require read-write memory. 2. In some systems, there is much more instruction memory than data memory, so a larger word size is used for instructions. 3. The instruction address bus may be wider than the data bus. Von Neumann Versus Harvard Parameters Von Neumann Architecture Harvard Architecture Definition The Von Neumann Architecture is Harvard Architecture is a modern an ancient type of computer type of computer architecture that architecture that follows the follows the concept of the relay- concept of a stored-program based model by Harvard Mark I. computer. Physical Address It uses one single physical It uses two separate physical address for accessing and storing addresses for storing and both data and instructions. accessing both instructions and data. Buses (Signal Paths) One common signal path (bus) It uses separate buses for the helps in the transfer of both transfer of both data and instruction and data. instructions. Number of Cycles It requires two clock cycles for It executes any instruction using executing a single instruction. only one single cycle. Von Neumann Versus Harvard Parameters Von Neumann Architecture Harvard Architecture Cost It is comparatively cheaper in It is comparatively more cost than Harvard Architecture. expensive than the Von Neumann Architecture. Access to CPU The CPU is not able to read/write The CPU can easily read/write data and access instructions at data as well as access the the same time. instructions at any given time. Uses This method comes to play in the This architecture is best for signal case of small computers and processing as well as personal computers. microcontrollers. big computer Requirement of Hardware As compared to Harvard This one requires more Architecture, Von Neumann hardware. It is because it Architecture requires lesser requires separate sets of data as architecture. It is because it only well as address buses for needs to reach one common individual memory. memory. Von Neumann Versus Harvard Parameters Von Neumann Architecture Harvard Architecture Requirement of Space This architecture basically This architecture comparatively requires less space. requires more space. Execution Speed The speed of execution of the The overall speed of execution of Von Neumann Architecture is Harvard Architecture is comparatively slower. It is comparatively faster. It is because it is not capable of because the processor can fetch fetching the instructions and data both instructions and data at the both at the same time. very same time. Controlling The process of controlling The process of controlling becomes comparatively simpler becomes comparatively complex with this architecture. It is with this architecture. It is because it fetches either because it basically fetches both instructions or data at any given instructions and data time. simultaneously at the very same time.