Digital System Design Chapter 7 PDF

Chapter 7 Digital System Design Figure 7.1. Tri-state driver. Figure 7.2. A digital system with k registers. Figure 7.3. Details for connecting registers to a bus. Figure 7.4. Using multiplexers to implement a bus. Figure 7.9. A digital system that implements a simple processor. Table 7.1. Op...

Chapter 7 Digital System Design Figure 7.1. Tri-state driver. Figure 7.2. A digital system with k registers. Figure 7.3. Details for connecting registers to a bus. Figure 7.4. Using multiplexers to implement a bus. Figure 7.9. A digital system that implements a simple processor. Table 7.1. Operations performed in the processor.  T0 T 1 T 2 T 3 y0 y1 y2 y3 2-to-4 decoder w1 w0 En 1 Q1 Q0 Clock Up-counter Clear Reset Figure 7.10. A part of the control circuit for the processor.  I0 I1 I2 I3 X X1 X2 X3 Y0 Y1 Y2 Y3 0 y0 y1 y2 y3 y0 y1 y2 y3 y0 y1 y2 y3 2-to-4 decoder 2-to-4 decoder 2-to-4 decoder w1 w0 En w1 w0 En w1 w0 En 1 1 1 Clock Function Register FRin f1 f 0 Rx1 Rx0 Ry 1 Ry 0 Function Figure 7.11. The function register and decoders. Table 7.2. Control signals asserted in each operation/time step. Figure 7.15. Timing simulation for the Verilog code in Figure 7.14.  B = 0; while A  0 do if a 0 = 1 then B = B + 1; end if; Right-shift A ; end while; Figure 7.16 Pseudo-code for the bit counter.  Reset S1 Load A B 0 0 0 1 s s 1 S2 S3 Shift right A Done 1 B B + 1 A = 0? 0 0 a0 Figure 7.17. ASM chart for the pseudo-code in Figure 7.16. 1 Figure 7.18. Datapath for the ASM chart in Figure 7.17.  Reset S1 LB 0 0 1 s s 1 S2 S3 EA Done 1 EB z 0 0 a0 1 Figure 7.19. ASM chart for the bit counter control circuit. Figure 7.21. Simulation results for the bit-counting circuit.  Decimal Binary 13 1 1 0 1 Multiplicand 11  1 0 1 1 Multiplier 13 1101 13 1101 143 0000 1101 1 0001111 Product (a) Manual method P = 0; for i = 0 to n – 1 do if bi = 1 then P = P+ A; end if; Left-shift A ; end for; (b) Pseudo-code Figure 7.22. An algorithm for multiplication. Figure 7.23. ASM chart for the multiplier.  LA 0 DataA LB DataB n n n L L Shift-left Shift-right EA E EB E register register A B Clock n 2n + Sum z b0 0 2n 2n Psel 1 0 Figure 7.24. Datapath circuit for the multiplier. 2n DataP EP E Register 2n P  Reset S1 Psel = 0EP 0 s 1 0 1 s S2 S3 Psel = 1EA EB Done 1 EP z 0 Figure 7.25. ASM chart for the 0 b0 multiplier control circuit. 1 Figure 7.27. Simulation results for the multiplier circuit.  15 00001111 Q 9 140 B 1001 10001100 A 9 1001 50 10001 45 1001 5 10000 1001 1110 (a) An example using decimal numbers 1001 101 R (b) Using binary numbers R = 0; for i = 0 to n – 1 do Left-shift RA ; if R  B then qi = 1 ; R = R– B ; else qi = 0 ; end if; end for; (c) Pseudo-code Figure 7.28. An algorithm for division.  Reset S1 R 0C n – 1 Load A Load B 0 1 s 0 1 S2 s Shift left R||A S4 S3 Done C C – 1 0 1 RB ? Shift 0 into Q Shift 1 into Q R R – B 1 0 C=0? Figure 7.29. ASM chart for the divider.  0 n LA DataA EB DataB Rsel 1 0 n n LR L L Left-shift w Left-shift E ER E EA E Register register register n n n an ” 1 B A EQ E Left-shift w cout + cin 1 register n n Clock Q R Figure 7.30. Datapath circuit for the divider.  Reset S1 Rsel = 0LR LC 0 1 s S2 ER EA S3 EQ Rsel = 1EC 0 1 0 s cout 1 S4 Done LR 1 0 z Figure 7.31. ASM chart for the divider control circuit.  B 1001 10001100 A Clock cycle R rr0 A/Q Load A, B 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 Shift left 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 , Q0 Shift left 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 2 , Q0 Shift left 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 3 , Q0 Shift left 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 4 , Q0 Shift left 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 5 Subtract, Q0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 6 Subtract, Q0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 7 Subtract, Q0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 8 Subtract, Q0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1 Figure 7.32. An example of division using n = 8 clock cycles.  Reset S1 LR Rsel = 0LC ER 0 1 s EA, ER0 S2 ER ER0 EA Rsel = 1 0 1 0 s cout 1 S3 Done LR EC 1 0 z Figure 7.33. ASM chart for the enhanced divider control circuit.  LA DataA EB DataB n n L Left-shift E EA E w Register register Clock n n B cout + cin 1 n 0 n Rsel 1 0 ER0 LR L rr 0 Left-shift w 0 0 ER E Q D register 1 qn ” 1 Q n n n” 1 r n ” 2  r0 n n R Q Figure 7.34. Datapath circuit for the enhanced divider. Figure 7.36. Simulation results for the divider circuit.  RAdd ER w1 w0 En 2-to-4 y0 y1 y2 y3 n Data E E E E Register Register Register Register Clock 0 z Ssel n EC E ES E LC L Down-counter Register k EB Sum k” 1 n + LA n n B EB A LA Figure 7.38. Datapath circuit for Div s Divider the mean operation. R Q Done n n M zz  Reset S1 LC Ssel = 0ES 0 s 1 S2 Ssel = 1ES EC 0 z 1 S3 0 LA EB s 1 S4 S5 Div Div, Done 0 1 zz Figure 7.39. ASM chart for the mean operation control circuit.  for i = 0 to k – 2 do A = Ri ; for j = i + 1 to k – 1 do B = Rj ; if B < A then Ri = B ; Rj = A ; A = Ri ; end if ; end for; end for; Figure 7.40. Pseudo-code for the sort operation.  Reset S1 Ci 0 Load registers 0 s 1 S2 A RiCj Ci S3 Ci Ci +1 Cj Cj +1 S4 B Rj S5 S6 B< A? 1 Cj Cj +1 Rj A 0 S7 Ri B S8 A Ri Figure 7.41. ASM chart for the sort operation. 0 C =K – 1? j S9 1 0 Done s 0 C =k – 2 1 1 i ?  DataIn ABmux n 0 1 WrInit n RData Rin0 E Rin1 E Rin2 E Rin3 E R0 R1 R2 R3 0 1 2 3 Imux ABData Ain E Bin E Rd Clock n DataOut 1 0 Bout  A B BltA Figure 7.42. A part of the datapath circuit for the sort operation.  0 2 2 LI L R LJ L R EI E Counter EJ E Counter Q Q Ci Cj Clock 2 = k” 2 zi 2 Csel 0 1 = k” 1 zj Cmux 2 2 RAdd Int 0 1 Imux 2 y0 Rin0 w0w1 y1 Rin1 y2 Rin2 WrInit En y3 Rin3 Wr 2-to-4 decoder Figure 7.43. A part of the datapath circuit for the sort operation.  Reset S1 LI Int = 0 0 s 1 S2 Int = 1Csel = 0Ain LJ S3 EI EJ S4 Bin Csel = 1Int = 1 S5 S6 1 EJ BltA Csel = 1Int = 1Wr Aout 0 S7 Csel = 0Int = 1Wr Bout S8 Csel = 0Int = 1Ain Figure 7.44. ASM chart for the control circuit. 0 zj 1 S9 0 Done s 0 1 1 zi  ff ff ff ff ff ff ff ff Clock ff ff ff ff ff ff ff ff Figure 7.47. An H tree clock distribution network.  tData Chip package pin Data A D Q Out B Clock tClock tod Figure 7.48. A flip-flop in an integrated circuit. Clock 3ns Data 4.5ns A 1.5ns B Figure 7.49. Flip-flop timing in a chip.  Data D Q D Q Data (asynchronous) (synchronous) Clock Q Q Figure 7.50. Asynchronous inputs.  VDD R VDD S Data R Data R R (a) Single-pole single-throw switch VDD (b) Single-pole double-throw switch with a basic SR latch Figure 7.51. Switch debouncing circuit.  Q = 0; R = A; while ((R – B) > 0) do R = R – B ; Q = Q+ 1; end while ; Figure P7.1. Pseudo-code for integer division.  5V 4 8 Ra Clock 3 7 (output) 555 Rb Timer 2 6 C1 1 5 0.01F Figure P7.2. The 555 programmable timer chip.