Rania Lec 2 PDF

Since the bus is defined as multi-master, managing all transaction transfers and control signals will be highly complex. Parallel Buses AMBA Bus AMBA is a comprehensive example of a parallel on-chip bus standard, offering a wide range of features. ➔...

Since the bus is defined as multi-master, managing all transaction transfers and control signals will be highly complex. Parallel Buses AMBA Bus AMBA is a comprehensive example of a parallel on-chip bus standard, offering a wide range of features. ➔ The standard defines two buses serving different roles: AHB (ARM High-performance Bus): A high-speed bus designed to connect fast peripherals, offering high clock frequencies and large throughput. It features complex hardware and is costly to implement. APB (ARM Peripheral Bus): A slower bus that is simpler in design compared to AHB, making it more cost-effective and easier to implement in hardware. AHP is faster than APB in range of [ 12x : 16x ] (speeds ratio must be an integer ) AMBA Architecture DMA Rule: Instead of the CPU handling memory communication, the DMA takes over. The CPU allows the DMA to master the AHB Bus when transferring data to or from memory. AHB/APB Bridge Rule: The AHB/APB bridge connects the high-speed AHB bus to the slower APB bus. It handles key tasks such as timing synchronization, split transactions, and packing/unpacking data between the AHB and APB buses. For the AHB, the bridge acts as a slave controlled by the CPU Speed, whereas for the APB, the bridge is the sole master with the speed of slaves. (bridge has two different clocks) AHB: Multi-master configuration. APB: Single-master configuration. Any transaction transfer needs 3 steps 1. Arbitration for the bus 2. Addressing the slave 3. Send data If the slave is not ready to communicate, it sends a signal to the bridge to split the transaction. The bridge will then handle the transaction in multiple stages A burst transaction involves sending multiple data items in a single transfer, improving efficiency by reducing overhead. AHB supports burst transactions, allowing multiple data words to be transferred in one go. However, APB does not natively support burst transactions, so the AHB/APB bridge breaks them into separate transactions for the APB. AHB Connectivity AHB is fast, parallel, multi-master, pipelined bus with support for burst and split transactions. The address is 32bits The higher bits for selecting the slave The lower part for selecting the register inside the slave  Name Type/Source/Destination Description HCLK Clock source The clock is an input to all elements in an AHB system and is assumed to come from some external clock generator. HRESET_n Reset controller AHB bus reset, active LOW. (duration = 16clk) HADDR[32:0] Output from Master System address bus which indicates the address to be used for a transfer. HTRANS[1:0] Output from Master which shows the type of transfer to be done. Transfer types→ NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY. HWRITE Output from Master Transfer direction. Indicates a write transfer when HIGH, and a read transfer when LOW. HSIZE[2:0] Output from Master Size of the transfer. This must be in terms of words indicate the size of the read or write transfer to be performed. HPROT[3:0] Output from Master Memory access protection type. This can be User mode (0) or privileged mode (1). involves opcode or data, and details about cacheability and write buffer properties. HWDATA[31:0] Output from Master Write data bus. Transfers data from bus master to bus slaves during write operations. HSELx Output from Master Slave select signal. This is a combinatorial decode of the address Input to Decoder bus. It indicates that the current transfer is intended for the selected slave. HRDATA[31:0] input to Master Read data bus. Transfers data from bus slaves to bus master during read operations. HREADY Output from each slave Transfer is completed signal, generated by an alternate slave. When HIGH, indicates that a transfer is complete. Semi-synchronous HRESP[1:0] Output from Slave Transfer response. This provides additional transfer status information. The response can be OKAY, ERROR, RETRY, or SPLIT. HBURST[2:0] Output from Master The master generates this bus to tell the system about the kind of burst it is performing - a single transfer, or a fixed, incrementing (incr) or wrapping burst. HBUSREQ Output from Master requesting that the master is granted control of the bus. input to the arbiter HGRANT Output from arbiter indicating that the master has been given the bus. input to the Master HLOCK/HMASTLOCK Output from arbiter a master will output HLOCK to show that the following transfer is locked (no one could interrupt the transaction and master the bus) HMASTER[3:0] Output from arbiter showing the number of the currently selected master. HSPLIT[15:0] output from split-capable show the arbiter which masters are currently waiting for a response slaves from that slave Pipelining A pipelined bus can perform each of three transaction phases simultaneously Burst Transaction reduce the time needed to access an amount of data and increase the throughput A special type of transaction that specifies a burst request to the slave, which may increment or decrement the given address. Reduces the need to send many sequential addresses through the bus. Reduces dynamic power consumption, as the computations for arbitration are minimized. May increase performance, since address decoding is handled at the destination. Often used by cache controllers when fetching a block of data from memory. 4-sequential words in Burst transaction 𝑨𝒓𝒃𝒊𝒕𝒓𝒂𝒕𝒊𝒐𝒏 → 𝒂𝒅𝒅𝒓𝒆𝒔𝒔𝒊𝒏𝒈 → 𝒘𝒐𝒓𝒅𝟏 (𝒊𝒏𝒄𝒓) → 𝒘𝒐𝒓𝒅𝟐 (𝒊𝒏𝒄𝒓) → 𝒘𝒐𝒓𝒅𝟑 (𝒊𝒏𝒄𝒓) → 𝒘𝒐𝒓𝒅𝟒 (𝟔𝒄𝒍𝒌) 4-sequential words in a single transaction 𝟒 ∗ (𝑨𝒓𝒃𝒊𝒕𝒓𝒂𝒕𝒊𝒐𝒏 → 𝒂𝒅𝒅𝒓𝒆𝒔𝒔𝒊𝒏𝒈 → 𝒅𝒂𝒕𝒂) (𝟏𝟐𝒄𝒍𝒌) Burst Used to fill buffers of peripherals with sequential data Write Read Trace the above timing diagrams😊 When the Ready signal is low → the data is held for the next clock cycle (write/Read) Split Transaction Primary Goal of Split Transactions: To improve bus performance in scenarios where long transactions are required (slave is not ready). Without Split Transactions: A master holds the bus while waiting for a response (e.g., communication with APB peripherals), preventing other masters (like DMA) from using the bus. With Split Transactions: The master issues a request, releases the bus, and waits for a notification, allowing other masters to use the bus during the wait time. Stages of Split Transaction 1. Transaction Initiation: The master starts the transaction as usual. 2. Slave Not Ready: If the slave is not ready, it asserts a split signal and remembers the active master (information provided by the arbiter). 3. Bus Reallocation: The arbiter grants the bus to other masters, allowing them to use it. 4. Notification: The slave asserts the HSPLIT signal to the arbiter, indicating which master can resume the transaction. 5. Bus Grant Restoration: The arbiter restores the bus grant to the interrupted master, allowing it to continue the transaction. APB APB (ARM Peripheral Bus): A slow, parallel bus with no support for pipelining, burst, or split transactions, and it has a single master (bridge). Speed Limitation: Peripherals connected to APB operate at lower speeds (up to 12x slower than AHB) to avoid wasting power and chip space. Legacy Design: Similar to buses used in 8-bit microcontrollers, as many of these peripherals are legacy devices built with older technologies. Data Width Mismatch: The data width of APB differs from AHB, so the bridge handles the splitting and merging of bytes/words to ensure compatibility (This implies the bridge has an internal buffer.). Write transfer From bridge to slave APB Write Operation (2-Clock Cycle Process): 1. Address Phase (1st Clock): The master sends the address, control signals, and data to the bridge, which forwards them to the peripheral. 2. Data Phase (2nd Clock): The peripheral receives and processes the write request, storing the data. Since APB lacks pipelining, each transfer takes two clock cycles. PSEL (Peripheral Select): Selects the target peripheral during the address phase to ensure only the chosen peripheral responds. PENABLE (Peripheral Enable): Activates the data phase, signaling the peripheral to process the read/write transfer. Here the address is taken at T3 (PSEL = 1) and takes one cycle to decoding Data is taken at T4 (PENABLE = 1) If PCLK = 10MHz, the actual data throughput is 5MHz, cause data is held by 2 clock cycles. Read Transfer Also, the Read operation takes 2cycles Note: The address/data buses are connected to all slaves, meaning every slave can receive or send data. However, the control signals(sel , en) are one bit for each slave, indicating which specific slave is involved in the transaction. Serial Buses RS-232C USB I2C RS-232C History Originally intended as an electrical specification to connect computer terminals to modems Defines the interface between a DTE and a DCE DTE = Data Terminal Equipment (terminal) → Computer , printer DCE = Data Communications Equipment (modem) → Network Interface Cards , Modem , Cellular Base Stations A “modem” is sometimes called a “data set” A “terminal” is anything at the “terminus” of the connection VDT (video display terminal), computer, printer, etc. RS-232C RS-232C Specifications Data Rate: o The maximum specified data rate is 20 Kbits/s with a maximum cable length of 15 meters. o It is common to push the RS-232C interface to higher data rates. o Data rates of up to 1 Mbit/s can be achieved, but only with shorter cables. Configuration: o Serial, point-to-point communication (one to one) Serial Data Transmission There are two main modes of serial data transmission: 1. Asynchronous: o The transmitting and receiving devices are not synchronized (must use the same baud rate) o A clock signal is not transmitted alongside the data. 2. Synchronous: o The transmitting and receiving devices are synchronized. o A clock signal is transmitted along with the data, which is used to synchronize the devices. Note: Most (but not all) RS-232C interfaces operate in asynchronous mode. Asynchronous Data Transmission Data Transmission: Data is transmitted on the TD (Transmit Data) line in packets, typically consisting of 7 or 8 bits. Framing: Each packet is framed by: o A start bit (0) at the beginning. o A stop bit (1) at the end of the packet. Parity Bit (Optional): o A parity bit can optionally be inserted just before the stop bit to provide error checking. o The parity bit ensures even parity or odd parity with the data bits in the packet: ▪ Even parity: The total number of bits equal to 1 must be an even number. Data is initially referred to as a packet. After adding the start and stop bits, it is called a frame. Frame = { Start , Data , Parity , Stop } 1’s and 0’s in RS-232C A “1” is referred to as a “mark”. A “0” is referred to as a “space”. The idle state of an RS-232C line is a 1 (mark). This idle state is called “marking the line”. The voltage levels on an RS-232C line are not a major concern for us and are considered a separate topic. Data Transmission Example Plot of the asynchronous RS-232C transmission of the ASCII character ‘a’ with odd parity: a = 0b1100_001 → after adding odd parity = 0b1100_001_0 𝒑𝒂𝒄𝒌𝒆𝒕 𝒔𝒊𝒛𝒆 𝟕 𝑫𝒂𝒕𝒂 𝑬𝒇𝒇𝒊𝒄𝒊𝒆𝒏𝒄𝒚 = = 𝒇𝒓𝒂𝒎𝒆 𝒔𝒊𝒛𝒆 𝟏𝟎 Universal Asynchronous Receiver Transmitter (UART) Converts parallel data into a serial format. The UART features both a transmission engine and a reception engine, which can function simultaneously. The UART's operations are managed through software by accessing various registers using the CPU's input and output instructions. Used to convert the data to serial bits to deal with RS-232S Adding the parity bit at the end of the data saves time in computing the parity (cumulative XOR). Instead of performing XOR on the parallel data, which can be time-consuming, the parity computation is overlapped with the process of converting data from parallel to serial format (less overhead). Universal Serial Bus (USB) UART was designed to replace the wide range of serial protocols that were prevalent in PCs and embedded systems at the time of its creation. It achieved significant success in PCs and continues to be used in embedded systems, although it faces competition from other protocols. I²C: A notable competitor, featuring simplicity with only data and clock lines. Commonly used for boot control, such as when the CPU communicates with external ROM. CAN, LIN, and others: Prominent competitors in the automotive industry, offering features like guaranteed service and support for multiple masters. USB transmits data using a differential unipolar non-return-to-zero (NRZ) encoding scheme. Unipolar → no -Ve voltage Logic 0 → Zero volt & logic 1 → +Ve Volt Non-return to zero → logic 1 remains at a high level throughout the bit duration Differential Signaling: Data is sent using two lines, D+ & D-. A large difference between the lines represents logic '1,' while a small difference represents logic '0,' making it reliable and noise-resistant. Universal Serial Bus (USB) is a synchronous serial protocol designed for low to medium-speed data transmission. USB 1.0: o Full-Speed: 12 Mbps o Low-Speed: 1.5 Mbps USB 2.0: o Maximum signaling rate: 480 Mbps (effective throughput ~35 Mbps) USB 3.0: o Maximum signaling rate: 5 Gbps (effective throughput ~625 Mbps) Typical Devices: Keyboards, mice, joysticks, speakers, and other low to medium-speed I/O devices. The maximum signaling rate is higher than the effective throughput because additional bits are used like framing, synchronization, and error detection/correction. These overhead bits reduce the portion of the signaling rate available for actual data transmission, similar to the 0.7 efficiency factor mentioned earlier. USB Technical Details: Master-Slave Structure: o The USB system has one master (usually a PC), though some smartphones can act as both master and slave. o The master is called the host, while slaves are called functions. Tree Structure: o The system is organized as a tree, with hubs acting as nodes to provide connectivity. Communication: o Functions cannot initiate communication; only the master can do so. o Communication is always initiated by the host, as there are no interrupts; data is received from functions via polling. Hot Plugging: o USB supports "hot plugging and unplugging," enabling devices to be connected or disconnected without restarting the system, provided the software is well-designed. Device Support: o Up to 128 devices can be connected simultaneously using hubs. HUB 😊 USB Physical Interface: Differential Signaling, Half-Duplex: USB uses differential signaling, meaning data is transmitted using two lines (D+ and D-) with opposite signals. It operates in half-duplex, meaning data can flow in one direction at a time. Input: USB transmits data as a binary stream. NRZ with Bit Stuffing: The data uses Non-Return-to-Zero (NRZ) encoding, and bit stuffing is applied by adding a zero after a sequence of 6 consecutive ones. This is done to maintain synchronization and avoid long strings of identical bits that could cause clock drift. Differential Encoding (NRZI): o A zero is represented by a transition in the signal. o A one is represented by no change in the signal. o In USB, these transitions are referred to as J (transition) and K (no transition). Special Condition for Synchronization: If both the D+ and D- lines are in the same state (both high or both low), it signals a special condition, which is used for synchronization. The synchronization pattern in USB communication consists of an 8-bit sequence designed to synchronize the receiver with the transmitter. This sequence is typically seven consecutive 0s followed by a single 1. The synchronization pattern helps the receiver align with the transmitter's clock. After NRZI encoding, the synchronization pattern is converted into a clock signal that represents the bit duration, allowing the receiver to correctly read the data. After encoding the output is D+ , D- Data Formatting in USB: Data is transmitted in packets, and each packet consists of the following fields: Start of Packet (SOP): The sync pattern, 8 bits (7 zeros followed by 1 one), used for synchronization. Packet ID (PID): An 8-bit field that identifies the type of packet (data , address , token…..) It includes 4 unique bits. Address Field: An 11-bit field, where: o 7 bits are used for the USB device address o allowing up to 128 devices on the bus; the host always uses address 0 o 4 bits are reserved for internal use by the USB device. Frame Number Field: An 11-bit field that is incremented by the host for each frame. Data Payload: The actual data being transmitted, with a maximum of 1023 bytes for high-speed connections. CRC (Cyclic Redundancy Check) Bits: o 5 bits for the address field. o 16 bits for the data field, used for error checking. End of Packet (EOP) Strobe: A single-ended signal that indicates the end of the packet (its duration based on speed) Additional Notes: Not all USB packets contain all of these fields. However, every packet will have at least the SOP, EOP, and PID fields. Token packets are a special type of packet that do not include a data field.