BERG 2133 Analogue Electronics Assignment PDF

Fakulti Teknologi dan Kejuruteraan Elektronik dan Komputer (FTKEK) Universiti Teknikal Malaysia Melaka ASSIGNMENT BERG 2133- ANALOGUE ELECTRONICS Date of Submission: Week 15 No. of students / group: Maximum: 4 s...

Fakulti Teknologi dan Kejuruteraan Elektronik dan Komputer (FTKEK) Universiti Teknikal Malaysia Melaka ASSIGNMENT BERG 2133- ANALOGUE ELECTRONICS Date of Submission: Week 15 No. of students / group: Maximum: 4 students/group 1.1 OBJECTIVE The objective of the assignment is not simply to create a working circuit but to learn about circuits. So, as you progress through the assignment, try to understand the role of each component, and how the choice of component value influences the operation of the circuit. Several questions can be asked: Why is this resistor here? Why were this particular integrated circuit chosen? How could the system be improved? All this question required to be answered in the discussion section with references cited. It is only when you can answer such questions that you will truly understand the assignment and progress towards designing your own circuits. All resistors from the simulations are required to use from standard value resistor (values that are available in the market). Hence, the percentage of error between, calculation to simulation, and simulation to experiment (for Q1) need to be presented in the discussion part. 1.2 PROCEDURES Each group is required to do TWO (2) questions. Please refer to Table 1 for assignment trigger combination. 1.2.1 QUESTION 1 (CALCULATION, SIMULATION AND EXPERIMENT) An audio preamplifier is to be developed for use in a small portable public address. The preamplifier will have a microphone input, and its output will drive as amplifier. As an electronic engineer, you have been asked to design a complete circuit of a preamplifier to operate with a peak input signal range and the minimal Voltage Gain stated in Table 1. Your design should involve discrete components only. Please also include the Bode plot of the design circuit. Hint: The preamplifier is a multistage amplifier that has common-emitter NPN (2N3417) with voltage divider bias at the first stage and common emitter NPN (2N3904) with voltage divider bias at the second stage. (Set β = 150 for both transistors) Table 1 Group Trigger Peak input signal (mV) Voltage Gain (Vo/Vin) 1 T1 40 90 2 T2 45 100 3 T3 50 110 4 T4 55 120 5 T5 60 130 6 T6 65 135 7 T7 70 140 8 T8 75 150 9 T9 80 160 10 T10 85 170  Fakulti Teknologi dan Kejuruteraan Elektronik dan Komputer (FTKEK) Universiti Teknikal Malaysia Melaka 1.2.2 QUESTION 2 (ONLY CALCULATION AND SIMULATION) (a) Besides BJT, a Field Effect Transistor (FET) is also widely used as input amplifier in electronic instrumentations. Design of a common source FET amplifier bias circuit for voltage divider configuration as shown in Figure 1 by using the given amplifier specification. The other specification of the circuit is stated in Table 2. FET Amplifier specification: R1 = 9R2; VGSQ = -2 V; IDSQ= 3 mA; AVmid = −5; AVs(mid)= −4.5. Table 2 Group Zi (kΩ) fLS (Hz) fLC (Hz) fLG (Hz) 1 41 40 2.5 3 2 42 41 3.0 4 3 43 42 3.5 5 4 44 43 4.0 6 5 45 44 4.5 7 6 46 45 5.0 8 7 47 46 5.5 9 8 48 47 6.0 10 9 49 48 6.5 11 10 50 49 7.0 12 11 51 50 7.5 13 12 52 51 8.0 14 13 53 50 8.5 15 40 V RD CC CG Rsig 6 kΩ + RS CS Vs _ Figure 1  Fakulti Teknologi dan Kejuruteraan Elektronik dan Komputer (FTKEK) Universiti Teknikal Malaysia Melaka (b) Referring to the circuit designed in Q2(a), sketch a frequency response using a Bode Plot and determine the bandwidth of the amplifier for the given capacitive elements. Capacitive elements of the circuit: Cds = 6 pF; Cgs = 2 pF; Cgd = 4 pF; Cwi = 8 pF, Cwo = 9 pF 1.3 EVALUATION Generally, the assignment will be evaluated according to Table 3, which is contributed from the assessments of the report and presentation. Table 3: Assessment Percentage. Criteria Percentage (%) CLO 1 5% CLO 2 10% CLO3 5% Total 20% The question must be answered clearly with the help of diagrams, if possible. The report should contain: Introduction Theoretical Explanation or Literature Review Results Analysis and Discussion Conclusion References Breakdown marks for your discussion and analysis is determined as in Table 4, Table 4: Discussion and Analysis Assessment Scheme (CLO1/PO2). Criteria Marks Analyze the performance of the design circuit 15 Discuss the performance of the design circuit 15 Compare the results between simulation, practical 15 and theoretical Sub Score /45 Normalization /5 Breakdown marks for your assessment scheme is determined as in Table 5,  Fakulti Teknologi dan Kejuruteraan Elektronik dan Komputer (FTKEK) Universiti Teknikal Malaysia Melaka Table 5: Design Assessment Scheme (CLO2/PO3). Criteria Marks Simulation (Design 1) Selection of component values 5 Justification of the component values 5 Names and schematic symbols 5 Construct simulation circuit from a schematic 5 Functionality of the designed circuit 10 Simulation (Design 2) Selection of component values 5 Justification of the component values 5 Names and schematic symbols 5 Construct simulation circuit from a schematic 5 Functionality of the designed circuit 10 Hardware (Design 1) Tidy circuit layout & soldering outlook 10 The functionality of the designed circuit 10 Sub Score /80 Normalization /10 The allocation marks for report writing assessment scheme is listed in Table 6. Table 6: Report Writing Assessment Scheme (CLO3/PO10). Criteria Marks Format and Organization 12 Delivery of Contents 20 Table and Figures 12 Grammar and Spelling 4 Sub Score /48 Normalization /5  Fakulti Teknologi dan Kejuruteraan Elektronik dan Komputer (FTKEK) Universiti Teknikal Malaysia Melaka REPORT SUBMISSION The final report should be completed by Week 14 (hardcopy) and also uploaded to ULEARN (softcopy). It is highly encouraged for any group to submit their report before the submission week. A penalty will be given in the form of marks deduction for any late submission. Hardware circuit must be submitted together with the report. PLEASE TAKE NOTE, PLAGIARISM IS A SERIOUS MISCONDUCTANCE AND WILL BE GIVEN ZERO MARKS!!!