Computer Architecture Inputs-outputs 2024/2025 PDF

BADJI MOKHTAR-ANNABA UNIVERSITY ‫جامعة باجي مختار – عنابـــــــــــــــة‬ FACULTY OF TECHNOLOGY ‫كلية التكنولوجيا‬ COMPUTER ENGINEERING DEPARTMENT ‫قسم مهندس في اإلعــــــــــــــالم اآللــــــــــــ...

BADJI MOKHTAR-ANNABA UNIVERSITY ‫جامعة باجي مختار – عنابـــــــــــــــة‬ FACULTY OF TECHNOLOGY ‫كلية التكنولوجيا‬ COMPUTER ENGINEERING DEPARTMENT ‫قسم مهندس في اإلعــــــــــــــالم اآللــــــــــــــي‬ Chapter 3 Inputs-outputs Organs linked to an I/O operation and I/O Modes Dr. MECHERI K. ARCHI2 S3 2024/2025  PLAN 1. Introduction 2. Generalities (Organs linked to an I/O operation) 3. Peripheral access interfaces (exchange units) 4. I/O modes 2  1. Introduction  Input-output management represents a very important function of the computer: communication.  These are activities that allow the information exchange between peripherals, processor and main memory.  The communication function is very complex and penalizing for the processor, in fact, it involves several modules that must be combined harmoniously. 3  2. Generalities Peripherals(3) Peripheral access interfaces (4) (exchange units) In addition to the processor (1) and the MM (2), the organs linked to an I/O operation are: Driver(6) Buses (5) allow information transport 4  2. Generalities Peripherals (See e-learning platform) Are hardware devices used to exchange information between the computer and its environment. They can be input, output or permanent storage devices. https://www.pmtic.net/contenu-en-ligne/environnement- 5 numerique/la-machine/l-ordinateur/recapitulons/les-peripheriques  2. Generalities Driver The program that manages an input-output operation is called a driver. This software knows all the technical characteristics of the device and is specific to this device. Thus, a user working with word processing software clicks on an icon to trigger the printing of a document. This click activates the printer driver, which receives the data to be printed. The driver installed in the OS then manages the printing (not the word processing software). For carrying out exchanges, a user program does not communicate directly with the device but with the driver of this device. 6  2. Generalities BUS A bus is a set of wires connecting several components (processor, cache, memory, I/O peripheral, etc.). - There is only one communication bus between different components in the Von Neumann architecture (fig. 1). Processor Memory I/O Communication bus 7  2. Generalities BUS Current machines use several and different individualized buses (fig. 2. Architecture of a recent machine). Main Bus, system bus or FSB (Front Side Bus), is the processor's only means of communication. Faster, wider Northbridge, responsible for distributing information between processor, memory, video card and the rest of components via a second circuit, Southbridge, in charge of the various I/O. 8  2. Generalities BUS The north bridge and the south bridge are sometimes located in the same box, the “chipset”. The trend is towards integrating these circuits into the processor. Advantages: Reduction of congestion and energy consumption, improved performance due to the geographical proximity of circuits. 9  2. Généralités Bus Most buses are characterized by a three-part structure: Address bus. carries the addresses used to designate an element or a memory location to communicate with the main memory. Its width has evolved: 16, 20, 32, 36, and 42 bits. It is unidirectional because it is the processor that indicates an address to the other components. Data bus. allows information (data and instructions) to be transferred from one component to another. Its width directly influences the flow of information available on the bus. Its standard width is 64 bits. It is bidirectional. Control bus. It carries control signals indicating the type of operation desired (memory reading or writing, video access, etc.). It is bidirectional so that the computer components it connects can communicate if necessary. 10  3. Peripheral access interfaces An input-output operation involves exchanging information between internal components and peripherals. To carry out these exchanges, special components are available, the exchange units (I/O controllers), in addition to the expansion buses. 11  3. 1. Exchange units or I/O controllers The task of I/O controller, placed between the bus and the peripheral, is :  to drive the I/O operation instead of the processor;  to format data and temporarily store it to adapt its format and the speed of its transfer between communication bus and peripheral ;  to allow the connection of various peripheral models via a standardized external interface (old parallel and serial interfaces, interfaces PS/2, SCSI, USB, FireWire…). See chapter 1 12 3. 1. Exchange units or I/O controllers I/O controllers and Buses The input/output controller is either located inside a chipset or connected to it via a specific bus (PCI bus, PCI express, etc.). It is sometimes on a removable I/O card, connected to the CD/DVD drive specific bus by a connector. Hard disk fig. 3: Simplified structure of a recent Macintosh type computer. 13 3. 1. Exchange units or I/O controllers I/O controllers and Buses The graphics controller transforms display commands sent by the processor into signals for a video monitor. Commands first pass through the north bridge, which puts them into a format compatible with the specifications of the PCI-express bus to which a video card is connected. On the south bridge there are specific controllers, USB and disks, allowing dialogue with the corresponding peripherals. There is also a PCI-express and PCI controller for connecting various external controllers. 14 3. 1. Exchange units or I/O controllers I/O controller and peripheral On the computer side: Each controller contains: - circuits for interfacing with a bus (PCI or PCI-express), - a control logic to drive the peripheral (decode the @ and the control lines), - an internal memory to store the data, associated with control registers and, - a standard external interface to connect the peripheral. (Figure 4) 15 16 3. 1. Exchange units or I/O controllers I/O controller and peripheral On the peripheral side: we find external interface, as well as control logic to work directly with the hardware (sending commands to mechanical parts, adapting electrical signals, etc.) Ex. Interface externe (prise et fiche VGA) 17 3. 1. Exchange units or I/O controllers Addressing a controller There are two ways to address an I/O controller : We can see it as a specific component that is accessed using a particular signal. The controller is part of the processor address space as shown in Figure 5. In this hypothesis, we address an exchange unit as we address a memory box. 18 3. 1. Exchange units or I/O controllers Addressing a controller An address is deposited on the @ bus, part of this @ is handled by a selection circuit which allows to select a box (memory or an exchange unit). In figure 5, three wires are reserved for the selection of a box (access to 8 different boxes). 19 3. 1. Exchange units or I/O controllers Functional structure of an I/O controller An exchange unit is organized around several addressable registers (figure 6). State register : Each state is characterized by a numerical value available in the status register. Ex. a printer that is out of paper sends a signal to the controller which loads the status register with the value corresponding to this state; Data register : Contains data exchanged between memory and the exchange unit. 20  3. 1. Exchange units or I/O controllers Functional structure of an I/O controller Example: to perform a write operation on a printer, this sequence can be executed: processor places the @ of the status register on the @ bus. This @ is composed of the @ of the box on one hand, and the @ of the register in the box on the other hand; processor reads the status register; if the contents of the register indicate that the printer is free, the processor addresses the data register; processor places data to be printed on the data bus. Data is now available for the printer; exchange unit will position the necessary signals triggering the physical printing of the data on the printer. 21  PLAN 1. Introduction 2. Generalities (Organs linked to an I/O operation) 3. Peripheral access interfaces (exchange units) 4. I/O modes 22  4. I/O modes 4.1. Introduction An input-output operation request made by a user program is translated by the compiler into a call (SVC: SuperVisor Call) to a specific program: the driver. Thus, there are simultaneously two types of programs in MM: the programs of the operating system kernel (notably the drivers) and the user program. Since there is only one central processor, the programs must share this unique resource. 23  4. I/O modes 4.2. Context switching mechanism The mechanism for managing an I/O operation consists of: - suspending the execution of the user program in favor of driver program of I/O operation, then, - after processing the I/O operation, resuming the execution of the user program. This relies on hardware context switching mechanism. 24  4. I/O modes 4.2. Context switching mechanism A program that runs has the hardware processor, that is, all the processor registers (particularly the Program Counter: PC). When suspending the program (UserPrg) execution in favor of another (Drive), it is necessary to save this hardware execution context in memory in order to be able to resume execution later, where it was abandoned. This context being saved, we can load the registers with the execution context of the new program (Driver) and in particular: place in the PC the @ of the first instruction of this new program. The new program is then executed on the hardware processor. At the end of its execution the context of the first program (UserPrg) is restored to resume its execution. 25  There are two main I/O modes: UserPrg in execution : I/O request Inst1 Programmed mode: The (SVC) Inst2 …. information exchange operation I/O inst n-1 between the exchange unit (EU) Inst n………… and the MM is handled by the Save UserPrg context in processor: MM Processor occupied by by interrogation, the processor I/O is totally occupied by the I/O. Load Driver context from MM (OS) Or not? by interruption, the processor is partially occupied by the I/O. Process I/O operation Direct Memory Access (DMA) Load UserPrg context mode. The information exchange from MM UserPrg in execution : operation between the EU and Inst1 the MM is direct, without Inst2 …. processor intervention. I/O instn-1 END I/O Inst n………… 26  4. I/O modes 4.3. Inputs/outputs by interrogation In this exchange mode, the driver uses the central Transfer not processor entirely to control Reading status register made exchanges with the peripheral. This mode is characterized by a permanent interrogation of EU by the processor. Status test The processor reads the status Transfer done register and tests the bits concerned by the exchange. Reading a piece of data Following the transfer, the received data is read or written. Processing data This mode is designated by: status test, polling (scrutation), busy waiting (attente active). 27  4. I/O modes 4.3. Inputs/outputs by interrogation Advantages Very easy to manage at the EU level because it is completely passive, simply responding to processor requests. Disadvantages Forces the processor to busy waiting during the entire operation, preventing it from performing other tasks (decreased performance). It can therefore only be used for devices with a short response time and transferring little data, such as a mouse that is polled regularly (e.g. every hundredths of a second) to update the position of the pointer. 28  4. I/O modes 4.3. Inputs/outputs by interrogation Example : of a printer driver using a serial card (exchange unit). EU has a status register and a data register that is one byte (one character) wide. UserPrg is the Word software, and the user decides to print a character file. The driver executes the algorithm below. Algorithme PRINT read status-register ; repeat while device_busy do read status-register ; endWhile; write a character in data register; Until there are no more characters to print. 29  WordPrg in execution : Word is running. When the user Inst1 clicks the print icon, this action Inst2 …. results in an SVC call to the (1) Driver Call(SVC) Print Inst n-1 printer driver (1). Inst n………… The driver must have the (2) Save Word Prg Context in processor, so it is necessary to MM Processor save the execution hardware totally busy context of the Word program (2) Load Driver context from by I/O and load the driver context into MM(SE) Word cannot be used the processor(2). At the end of printing, the driver (3) Process I/O operation reloads the Word execution (Algo PRINT) context into the processor, which then resumes execution (4) Load Word Prg context at the point where it was from MM WordPrg in execution : Inst1 interrupted. (4). Inst2 …. END I/O Print Instn-1 Inst n………… 30  4. I/O modes 4.3. Inputs/outputs by interrogation Example : of a printer driver using a serial card (exchange unit). The execution time diagram shows that if the processor is constantly busy, it is not the user who benefits: Word cannot work while printing is in progress and therefore characters cannot be entered during printing. CU occupation System CU Peripheral 31  4. I/O modes 4.4. Inputs/outputs by interruption In order to improve the performance of the computer when performing an I/O operation, the EU uses the interrupt mechanism to signal that it is ready. Thus, each time a character is printed, the printer signals it to the EU which issues an interrupt to the processor. To handle interrupts, the OS has a set of interrupt handler programs. When an interrupt is received, the running program is stopped in favor of the interrupt handler program. 32  4. I/O modes 4.4. Inputs/outputs by interruption Execution timing scheme (e.g. Printing):  Word is running and the user clicks on the print icon.  The driver is alerted (switching) and checks that the printer is free. If the printer is free, the driver loads the data register and the printing of the first character is launched.  From this moment, the processor is free. It does not have to check if the printer is ready because it will be warned by an interrupt. The processor can therefore be returned to the Word program (switching) which will allow the entry of characters while a character is being printed.  At the end of the character printing, Word execution is interrupted in favor of the interrupt management program (switching). This processing ends with a call to the driver (switching) which checks if there are still characters to print. If so, it places a new character in the data register and the printing of the next character begins.  The processor is again assigned to Word (switching). 33  Word in execution : Inst1 Driver call (SVC) Inst2 …. Inst PRINT …. Other Inst n………… characters Printing support by driver. Processor Busy Character i printing started No character Processor free (returned to Word program ) End printing of character i End printing INTERRUPTION Processor interrupted 34  4. I/O modes 4.4. Inputs/outputs by interruption The user permanently owns the processor except during periods when the processor is assigned to the interrupt and driver management program. This printing processing is called background processing since the user has the impression of working permanently with Word, including during the printing phase. 35  4. I/O modes 4.4. Inputs/outputs by interruption Advantages The processor no longer waits for the device. Disadvantages  Time loss in data transfers.  Relatively busy processor since it has to manage the transfer operation. It is therefore a mode reserved for short data transfers. 36  4. I/O modes 4.5. Direct Memory Access I/O When transferring large amounts of data, the previous two modes are inefficient, because the processor is busy with I/O operations and interrupts. To reduce the number of interrupts, another mode is used where the EU can work directly with the memory without going through the processor. This involves using a DMA (Direct Memory Access) controller. 37  4. I/O modes 4.5. Direct Memory Access I/O The DMA device is a hardware component that allows information transfers between main memory (MM) and EU without using the processor. I/O processing with DMA : 1. The Central Processor (Driver) initializes the DMA :  identification of the device concerned (p@ register),  direction of the transfer (command register),  address in MM of the first word to be transferred (word @ register) and,  number of words concerned by the exchange (nb counter). 2. The DMA performs the exchange 3. When the exchange is complete, the DMA signals to the processor the end of the I/O operation with an interrupt. 38  Peripheral Address bus Data bus Control bus EU Central Main Memory Command Buffer zone Processor (/data register) IRQ_DMA subroutine : register Transfer Check OK Interrupt Routine p@register …………………………….. Active I/O driver: component Initialize DMA : Word @ register (processor) p@ = peripheral address nb = number of bytes to transfer w@ = address of first byte in MM Counter (nb) direction = writing; DMA controller Launch DMA………………………………….. ……………………………………….. 1. Processor (Driver) initializes the DMA 2. DMA performs the exchange 3. DMA signals to the processor the end of the I/O operation by an interrupt. 39  4. I/O modes 4.5. Direct Memory Access I/O Example: To read several bytes from the disk and place them in memory: 1. After identifying the peripheral, the processor initializes the @ register of the DMA with the @ of the first memory location where the data is to be stored. 2. The counter is loaded with the number of bytes to be transferred. The processor sends the read command to the controller (via the control bus). 3. The controller retrieves the data from the peripheral and stores it in the data register. 4. It transfers it to memory via the data bus: 5. The first address is sent on the address bus with the first data (via the data bus) and a memory write signal (via the control bus). 6. Once the writing is done in the main memory, the address register is incremented, the counter is decremented and, 7. If the counter is not zero, the controller repeats the writing operation with the next data (step 3). 8. When all the desired information has been written to memory, the DMA controller notifies the processor of the end of the operation by an interrupt signal. 40  4. I/O modes 4.5. Direct Memory Access I/O Main Memory A PC's DMA controller manages 8 DMA channels: DMA1: Sound card DMA2: Floppy disk controller DMA3: parallel port (printer) DMA 2 DMA 3 DMA6: hard disk controllers DMA controller Each channel has an area in main memory (@ start, @ end) accessible for transfer. 41  4. I/O modes 4.5. Direct Memory Access I/O Advantages: DMA transfer is much faster than transfer with other modes. During the transfer, the microprocessor can perform other tasks. Disadvantages The processor and the DMA controller might need the buses at the same time (conflict). DMA is used extensively: - data transfer between memory and hard disk - data transfer to the graphics card or sound card, etc. 42  References 1. Alain Cazes, Joëlle Delacroix, ‘Architecture des machines et des systèmes informatiques, cours et exercices corrigés’. 4e édition, DUNOD, 2011. 2. Jean-François Lalonde ‘Les entrées- sorties : programmées, interruptions et DMA’ GIF-1001 Ordinateurs: Structure et Applications, Hiver 2017. 3. Gérard Blanchet, Bertrand Dupouy, « Architecture des ordinateurs , principes fondamentaux», 2013, Lavoisier, Paris. 4. Emmanuel Lazard, Université Paris-Dauphine, « Architecture de l’ordinateur » mars 2011. 5. Sylvain MONTAGNY ‘Architecture des ordinateurs’, cours, université Savoie. 6. Joëlle Delacroix ‘Entrées sorties’ cours 43