LPC 2148 Peripherals PDF

LPC 2148 peripherals Course handled by Dr.Saru Meena R. Assistant Professor Dept. of Electronics and Communication Engineering, Amrita School of Engineering...

LPC 2148 peripherals Course handled by Dr.Saru Meena R. Assistant Professor Dept. of Electronics and Communication Engineering, Amrita School of Engineering Amrita Vishwa Vidyapeetham Coimbatore  General purpose input and output (GPIO) § General-purpose input/output (GPIO) is a pin on an IC (Integrated Circuit) § It can be either input pin or output pin, whose behavior can be controlled at the run time § A group of these pins is called a port (Example, Port 0 of LPC2148 has 32 pins). § LPC2148 has two 32-bit General Purpose I/O ports : (a) PORT0 and (b) PORT1 Port 0 : § PORT0 is a 32-bit port § Out of these 32 pins, 28 pins can be configured as either general purpose input or output § 1 of these 32 pins (P0.31) can be configured as general-purpose output only § 3 of these 32 pins (P0.24, P0.26 and P0.27) are reserved. Hence, they are not available for use. Also, these pins are not mentioned in pin diagram 2  General purpose input and output (GPIO) § PORT1 is also a 32-bit port. Only 16 of these 32 pins (P1.16 – P1.31) are available for use as general-purpose input or output § Almost every pin of these two ports has some alternate function available § For example, P0.0 can be configured as the TXD pin for UART0 or as PWM1 pin as well § The functionality of each pin can be selected using the Pin Function Select Registers (PINSEL) Pin diagram of LPC 2148 3  General purpose input and output (GPIO) Pin Function Select Registers (PINSEL) § PINSEL registers are 32-bit registers. These registers are used to select or configure specific pin functionality. § There are 3 PINSEL registers in LPC2148: 1. PINSEL0 : - PINSEL0 is used to configure PORT0 pins P0.0 to P0.15. 2. PINSEL1 : - PINSEL1 is used to configure PORT0 pins P0.16 to P0.31 3. PINSEL2 : - PINSEL2 is used to configure PORT1 pins P1.16 to P1.31. § Any pin on the LPC2148 can have a maximum of 4 functions § In order to select one of the four functions, two corresponding bits of the PINSEL register are needed 4 General purpose input and output (GPIO) 5  General purpose input and output (GPIO) § There are two types of GPIO : (a) Slow GPIO and (b) fast GPIO Slow GPIO : § In slow GPIO mode, the access to GPIO registers is done through the VPB (VLSI Peripheral Bus) § The VPB clock is typically derived from the CPU clock (CCLK) but can be divided by a factor (default is 4) § This division makes GPIO operations slower compared to the fast mode § Slow GPIO operations can take more clock cycles due to the VPB divider Key characteristics of slow GPIO : § Accesses GPIO through VPB (divided clock). § Suitable for most standard GPIO applications. § Can be relatively slower due to the clock division 6  General purpose input and output (GPIO) Fast GPIO registers: § The fast GPIO is an enhanced version of GPIO access, introduced to speed up the GPIO operations. § In fast GPIO mode, the GPIO registers are accessed directly through the AHB (Advanced High-performance Bus), which runs at the CPU clock speed (CCLK) without any division. § Fast GPIO operations are much faster because the GPIO control is directly connected to the AHB bus. Key characteristics of fast GPIO: § Accesses GPIO directly through the AHB (no clock division). § Provides faster response for GPIO pin operations. § Suitable for time-critical applications where fast response is needed (e.g., toggling pins at high frequency) Thus, slow GPIO is slower due to clock division, while fast GPIO operates at the system clock speed and is used when speed is critical 7  General purpose input and output (GPIO) Slow GPIO registers: § IOxDIR (GPIO Port Direction control register) : This is a 32-bit wide register. This register individually controls the direction of each port pin. Setting a bit to ‘1’ configures the corresponding pin as an output pin. Setting a bit to ‘0’ configures the corresponding pin as an input pin. § IOxSET (GPIO Port Output Set register) : This is a 32-bit wide register. This register is used to make pins of Port (PORT0/PORT1) HIGH. Writing one to specific bit makes that pin HIGH. Writing zero has no effect. § IOxCLR (GPIO Port Output Clear register) : This is a 32-bit wide register. This register is used to make pins of Port LOW. Writing one to specific bit makes that pin LOW. Writing zeroes has no effect. § IOxPIN (GPIO Port Pin value register): This is a 32-bit wide register. This register is used to read/write the value on Port (PORT0/PORT1). But care should be taken while writing. Masking should be used to ensure write to the desired pin § x=0 or 1 ; 0 if port 0 is used and 1 if port 1 is used 8 General purpose input and output (GPIO) 9 General purpose input and output (GPIO) Configuring the pins as input or output : 10 General purpose input and output (GPIO) Configuring the pins as input or output : 11 General purpose input and output (GPIO) Configuring the pins as input or output : 12 General purpose input and output (GPIO) Configuring the pins as input or output : 13 General purpose input and output (GPIO) Configuring the pins as input or output : 14 General purpose input and output (GPIO) 15 General purpose input and output (GPIO) 16 General purpose input and output (GPIO) 17 Analog to digital converter (ADC) 18 Analog to digital converter (ADC) 19  Analog to digital converter (ADC) Registers associated with ADC : 1) ADxCR : ADC control register (size : 32 bit) x=0 or 1 depending upon the ADC module chosen x=0 if ADC0 is chosen ; x=1 if ADC1 is chosen AD0CR : Bits 7:0 – SEL These bits select ADC0 channel as analog input. In software-controlled mode, only one of these bits should be 1.e.g. bit 7 (10000000) selects AD0.7 channel as analog input 20  Analog to digital converter (ADC) Bits 15:8 – CLKDIV § The APB(ARM Peripheral Bus)clock is divided by this value plus one, to produce the clock for ADC § This clock should be less than or equal to 4.5MHz 21  Analog to digital converter (ADC) Peripheral clock (PCLK) : § CCLK → CPU clock (60 MHz) § 𝑓!"# = 12 𝑀𝐻𝑧 § 𝑓!"# → PLL block → CCLK = 60 MHz $$%& § CCLK → VPB DIV block → PCLK = ' § If PCLK has to be 60 MHz , y=1 (i.e.) the dividing factor in the VPB DIV block should be 1 § If PCLK has to be 30 MHz , y=2 (i.e.) the dividing factor in the VPB DIV block should be 2 22  Analog to digital converter (ADC) Bits 15:8 – CLKDIV § The APB(ARM Peripheral Bus)clock is divided by this value plus one, to produce the clock for ADC § This clock should be less than or equal to 4.5MHz Calculation : ($%& (+,-.+/,-01 #1!#2) § 4 = 𝐴𝐷𝐶 𝑐𝑙𝑜𝑐𝑘 = 4.5 𝑀𝐻𝑧 ($%& $(6 #1!#2 § PCLK = 60 MHz ; ∴ 𝑥 = 135 ; but this x is made to 14 so that ≤ 4.5 𝑀𝐻𝑧 4 § But to avoid the divide by zero error , LPC 2148 will add 1 to whatever value is being given in CLKDIV. ∴ 8 bit binary representation of 135 is loaded in CLKDIV ; CLKDIV = 0000 1101 § In short , value needed is 𝑥 = 145 ; value loaded is 𝑥 = 135 23  Analog to digital converter (ADC) Bit 16 – BURST Burst mode in the LPC2148 ADC allows for continuous conversions without the need for constant manual triggering § When burst =0 , the ADC waits for the user to tell it to start each time. It takes one reading, then stops. § Burst = 0 means the user must manually trigger the ADC to start each conversion, either by software (the user tell it to start) or using an external signal (like pressing a button) § The ADC converts the signal once and then stops. The user must issue another command for the next conversion. 24  Analog to digital converter (ADC) Bit 16 – BURST When BURST = 1, ADC works in burst mode § When burst mode is enabled, the ADC automatically samples and converts the selected analog input channels repeatedly without requiring the user to start each conversion individually § In simple terms, it's like setting the ADC to autopilot mode—once activated, it keeps converting analog signals into digital values continuously for the selected channels, instead of waiting for the user to say, "start a new conversion” § When Burst = 1, the START bits must be 000, otherwise the conversions will not start § In Burst mode, ADC does repeated conversions at the rate selected by the CLKS field for the analog inputs selected by SEL field § When Burst = 1, the START bits must be 000, otherwise the conversions will not start 25  Analog to digital converter (ADC) Bits 19:17 – CLKS Selects the number of clocks used for each conversion in burst mode and the number of bits of accuracy of Result bits of AD0DR. e.g. 000 uses 11 clocks for each conversion and provide 10 bits of result in corresponding ADDR register. 000 = 11 clocks / 10 bits 001 = 10 clocks / 9 bits § For 10 bit ADC , the smallest change in analog voltage (step size) = 010 = 9 clocks / 8 bits !.! = 3.2 𝑚𝑣 #$%& 011 = 8 clocks / 7 bits § If the input voltage is 0v, the digital output is 0. If the input voltage 100 = 7 clocks / 6 bits becomes 3.3mv, the digital output is 1. 101 = 6 clocks / 5 bits § Only if there is a change in input voltage by 3.2 mv, there will be a 110 = 5 clocks / 4 bits transition to the next value in digital output 26  Analog to digital converter (ADC) Bit 20 – RESERVED Bit 21 – PDN ; used to decide whether ADC is in power down mode or involved in conversion 0 = ADC is in Power Down mode 1 = ADC is operational Bit 23:22 – RESERVED Bit 26:24 – START When BURST bit is 0, these bits control whether and when A/D conversion is started 000 = No start (Should be used when clearing PDN to 0) 001 = Start conversion now 27  Analog to digital converter (ADC) 010 = Start conversion when edge selected by bit 27 of this register occurs on CAP0.2/MAT0.2 pin 011= Start conversion when edge selected by bit 27 of this register occurs on CAP0.0/MAT0.0 pin 100 = Start conversion when edge selected by bit 27 of this register occurs on MAT0.1 pin 101 = Start conversion when edge selected by bit 27 of this register occurs on MAT0.3 pin 110 = Start conversion when edge selected by bit 27 of this register occurs on MAT1.0 pin 111 = Start conversion when edge selected by bit 27 of this register occurs on MAT1.1 pin 28  Analog to digital converter (ADC) Bit 27 – EDGE This bit is significant only when the Start field contains 010-111. In these cases, 0 = Start conversion on a rising edge on the selected CAP/MAT signal 1 = Start conversion on a falling edge on the selected CAP/MAT signal Bit 31:28 – RESERVED 29  Analog to digital converter (ADC) ADxGDR (A/D Global Data Register) : § ADxGDR is a 32-bit register (x=0 or 1) § This register contains the ADC’s DONE bit and the result of the most recent A/D conversion Bit 5:0 – RESERVED Bits 15:6 – RESULT § When DONE bit is set to 1, this field contains 10-bit ADC result that has a value in the range of 0 (less than or equal to VSSA) to 1023 (greater than or equal to VREF). 30  Analog to digital converter (ADC) Bit 23:16 – RESERVED Bits 26:24 – CHN § These bits contain the channel from which ADC value is read. e.g. 000 identifies that the RESULT field contains ADC value of channel 0. Bit 29:27 – RESERVED Bit 30 – Overrun § This bit is set to 1 in burst mode if the result of one or more conversions is lost and overwritten before the conversion that produced the result in the RESULT bits § This bit is cleared by reading this register Bit 31 – DONE § This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the AD0CR is written § If AD0CR is written while a conversion is still in progress, this bit is set and new conversion is started 31  Analog to digital converter (ADC) AD0DR0-AD0DR7 (ADC0 Data Registers) § These are 32-bit registers. § They hold the result when A/D conversion is completed. § They also include flags that indicate when a conversion has been completed and when a conversion overrun has occurred AD0 data registers structure Bit 5:0 – RESERVED Bits 15:6 – RESULT § When DONE bit is set to 1, this field contains 10-bit ADC result that has a value in the range of 0 (less than or equal to VSSA) to 1023 (greater than or equal to VREF). Bit 29:16 – RESERVED 32  Analog to digital converter (ADC) Bit 30 – Overrun § This bit is set to 1 in burst mode if the result of one or more conversions is lost and overwritten before the conversion that produced the result in the RESULT bits § This bit is cleared by reading this register Bit 31 – DONE § This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read 33  Analog to digital converter (ADC) Steps in analog to digital conversion : § Configure the port pin to function as ADC § Configure the ADxCR (ADC Control Register) according to the need of application. § Start ADC conversion by writing appropriate value to START bits in ADxCR. (Example, writing 001 to START bits of the register 26:24, conversion is started immediately). § Monitor the DONE bit (bit number 31) of the corresponding ADxDRy (ADC Data Register) till it changes from 0 to 1. This signals completion of conversion § Read the ADC result from the corresponding ADC Data Register ADxDRy. E.g. AD0DR1 contains ADC result of channel 1 of ADC0. 34  Analog to digital converter (ADC) Steps in analog to digital conversion : 35  Analog to digital converter (ADC) Step 1 : PINSEL 1 register 36  Analog to digital converter (ADC) Step 2 : Enable the power/clock to ADC0 PCONP : Power control for peripheral register (32 bit register) 37  Analog to digital converter (ADC) Step 3 : Select channel 3 in AD0 ADOCR (Bits 7:0) 38  Analog to digital converter (ADC) Step 4 : Set the CLKDIV to 13 ADOCR AD0CR | = 13 6) and 0xFFFFF3FF If AD0GDR & = 0x80000000 is 1 , it val = (AD0DR3>>6) & 0XFFFFF3FF indicates that analog to digital conversion is Step 9 : Deactivate the ADC module by making START bits (bits complete ; else , it indicates that the analog 26 : 24) in AD0DGR as 000. This is done via. AND operation to digital conversion process is not yet between AD0CR and 0x F8FFFFFF completed AD0GDR & = 0xF8FFFFFF § When DONE =1 , the 10 bit A/D conversion result is available in bits 15 : 6 To visualize the result in terms of ON / OFF of 10 LEDs connected of AD0DR3. To visualize the result to port 1 (P1.16 to P1.25) , IOPORT1 = val