Messenger_creation_521142684051458.jpeg

## Static CMOS Logic ### CMOS Inverter * **CMOS inverter circuit:** * A simple, but important, example of a CMOS circuit * Also called a NOT gate * Consists of a PMOS and an NMOS transistor * PMOS is connected to $V_{DD}$ * NMOS is connected to ground * The g...

## Static CMOS Logic ### CMOS Inverter * **CMOS inverter circuit:** * A simple, but important, example of a CMOS circuit * Also called a NOT gate * Consists of a PMOS and an NMOS transistor * PMOS is connected to $V_{DD}$ * NMOS is connected to ground * The gate of both transistors are connected to the input * The drains of both transistors are connected to the output *Image of a CMOS inverter circuit with the following:* * *Input:* $V_{in}$ * *Output:* $V_{out}$ * *PMOS Transistor:* $V_{DD}$, p-channel * *NMOS Transistor:* Ground, n-channel * **CMOS Inverter Operation:** | $V_{in}$ | NMOS | PMOS | $V_{out}$ | | :------- | :----- | :----- | :-------- | | Low | OFF | ON | High | | High | ON | OFF | Low | * When $V_{in}$ is low, the NMOS is OFF and the PMOS is ON, so $V_{out}$ is pulled up to $V_{DD}$ (high) * When $V_{in}$ is high, the NMOS is ON and the PMOS is OFF, so $V_{out}$ is pulled down to ground (low) * **CMOS Inverter Voltage Transfer Curve(VTC):** *Image of a CMOS Inverter Voltage Transfer Curve plot with the following:* * *x-axis:* $V_{in}$ * *y-axis:* $V_{out}$ * *Curve:* A curve starting at ($0, V_{DD}$), decreasing until ($V_{DD}, 0$) * *Sharp transition region:* The region where the curve rapidly decreases * *Regions:* 5 regions with different transistor operation conditions * The VTC shows the relationship between the input and output voltages of the inverter. * The VTC can be divided into five regions, depending on the operating state of the NMOS and PMOS transistors: 1. **Region A:** NMOS is in cutoff, PMOS is in the linear region, $V_{out} = V_{DD}$ 2. **Region B:** NMOS is in cutoff, PMOS is in saturation, $V_{out} = V_{DD}$ 3. **Region C:** NMOS is in saturation, PMOS is in saturation, $V_{out} = V_{DD}/2$ 4. **Region D:** NMOS is in the linear region, PMOS is in saturation, $V_{out} = 0$ 5. **Region E:** NMOS is in the linear region, PMOS is in cutoff, $V_{out} = 0$ ### CMOS NAND Gate * **CMOS NAND gate circuit:** * Consists of two PMOS transistors in parallel and two NMOS transistors in series * The sources of the PMOS transistors are connected to $V_{DD}$. * The sources of the NMOS transistors are connected to ground. * The gate of the PMOS transistor and the gate of the NMOS transistor are connected to their respective inputs A and B * The drains of both transistors are connected to the output F *Image of a CMOS NAND gate circuit with the following:* * *Inputs:* A, B * *Output:* F * *PMOS Transistors:* p-channel, connected in parallel * *NMOS Transistors:* n-channel, connected in series * **CMOS NAND gate Operation:** | A | B | F | | :--- | :--- | :--- | | Low | Low | High | | Low | High | High | | High | Low | High | | High | High | Low | * If either A or B is low, at least one of the PMOS transistors will be ON, so $V_{out}$ is pulled up to $V_{DD}$ (high) * If both A and B are high, both of the NMOS transistors will be ON, so $V_{out}$ is pulled down to ground (low) * Therefore, the output F is LOW only when both inputs A and B are HIGH ### CMOS NOR Gate * **CMOS NOR gate circuit:** * Consists of two PMOS transistors in series and two NMOS transistors in parallel * The sources of the PMOS transistors are connected to $V_{DD}$. * The sources of the NMOS transistors are connected to ground. * The gate of the PMOS transistor and the gate of the NMOS transistor are connected to their respective inputs A and B * The drains of both transistors are connected to the output F *Image of a CMOS NOR gate circuit with the following:* * *Inputs:* A, B * *Output:* F * *PMOS Transistors:* p-channel, connected in series * *NMOS Transistors:* n-channel, connected in parallel * **CMOS NOR gate Operation:** | A | B | F | | :--- | :--- | :--- | | Low | Low | High | | Low | High | Low | | High | Low | Low | | High | High | Low | * If either A or B is high, at least one of the NMOS transistors will be ON, so $V_{out}$ is pulled down to ground (low) * If both A and B are low, both of the PMOS transistors will be ON, so $V_{out}$ is pulled up to $V_{DD}$ (high) * Therefore, the output F is HIGH only when both inputs A and B are LOW