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# Static CMOS Logic ## CMOS Inverter ### Circuit * NMOS: $V_{TN}$, $k_n' = \mu_n C_{OX}$ * PMOS: $V_{TP}$, $k_p' = \mu_p C_{OX}$ ### Transfer Characteristics * **Region A**: $V_{in} \le V_{TN}$, NMOS **OFF** * $I_{DSN} = 0$ * $I_{DSP} = 0$ * $V_{out} = V_{DD}$ * **Regi...

# Static CMOS Logic ## CMOS Inverter ### Circuit * NMOS: $V_{TN}$, $k_n' = \mu_n C_{OX}$ * PMOS: $V_{TP}$, $k_p' = \mu_p C_{OX}$ ### Transfer Characteristics * **Region A**: $V_{in} \le V_{TN}$, NMOS **OFF** * $I_{DSN} = 0$ * $I_{DSP} = 0$ * $V_{out} = V_{DD}$ * **Region B**: $V_{in} > V_{TN}$, NMOS **SAT**, PMOS **LIN** * $I_{DSN} = \frac{k_n'}{2} (\frac{W}{L})_n (V_{in} - V_{TN})^2$ * $I_{DSP} = k_p' (\frac{W}{L})_p [(V_{in} - V_{DD} - V_{TP})(V_{out} - V_{DD}) - \frac{1}{2}(V_{out} - V_{DD})^2]$ * $I_{DSN} = \mid I_{DSP} \mid$ * **Region C**: NMOS **SAT**, PMOS **SAT** * Neither transistor is in the linear region * Both transistors are in saturation * Point where $V_{in} = V_{out}$ * **Region D**: $V_{in} < V_{DD} + V_{TP}$, PMOS **SAT**, NMOS **LIN** * $I_{DSN} = k_n' (\frac{W}{L})_n [(V_{in} - V_{TN})V_{out} - \frac{1}{2}V_{out}^2]$ * $I_{DSP} = \frac{k_p'}{2} (\frac{W}{L})_p (V_{in} - V_{DD} - V_{TP})^2$ * $I_{DSN} = \mid I_{DSP} \mid$ * **Region E**: $V_{in} \ge V_{DD} + V_{TP}$, PMOS **OFF** * $I_{DSP} = 0$ * $I_{DSN} = 0$ * $V_{out} = 0$ ### Design for $V_{M} = V_{DD}/2$ $V_M$: Inverter Threshold Voltage Set $V_{in} = V_{out} = V_M = V_{DD}/2$ $I_{DSN} = \frac{k_n'}{2} (\frac{W}{L})_n (V_{M} - V_{TN})^2 = \frac{k_n'}{2} (\frac{W}{L})_n (\frac{V_{DD}}{2} - V_{TN})^2$ $I_{DSP} = \frac{k_p'}{2} (\frac{W}{L})_p (V_{M} - V_{DD} - V_{TP})^2 = \frac{k_p'}{2} (\frac{W}{L})_p (\frac{V_{DD}}{2} - V_{DD} - V_{TP})^2 = \frac{k_p'}{2} (\frac{W}{L})_p (-\frac{V_{DD}}{2} - V_{TP})^2 = \frac{k_p'}{2} (\frac{W}{L})_p (\frac{V_{DD}}{2} + V_{TP})^2$ $I_{DSN} = \mid I_{DSP} \mid$ $\frac{k_n'}{2} (\frac{W}{L})_n (\frac{V_{DD}}{2} - V_{TN})^2 = \frac{k_p'}{2} (\frac{W}{L})_p (\frac{V_{DD}}{2} + V_{TP})^2$ $\frac{(\frac{W}{L})_p}{(\frac{W}{L})_n} = \frac{k_n'}{k_p'} \frac{(\frac{V_{DD}}{2} - V_{TN})^2}{(\frac{V_{DD}}{2} + V_{TP})^2} = \frac{\mu_n C_{OX}}{\mu_p C_{OX}} \frac{(\frac{V_{DD}}{2} - V_{TN})^2}{(\frac{V_{DD}}{2} + V_{TP})^2} = \frac{\mu_n}{\mu_p} \frac{(\frac{V_{DD}}{2} - V_{TN})^2}{(\frac{V_{DD}}{2} + V_{TP})^2}$ If $V_{TN} = \mid V_{TP} \mid = V_T$: $\frac{(\frac{W}{L})_p}{(\frac{W}{L})_n} = \frac{\mu_n}{\mu_p} (\frac{\frac{V_{DD}}{2} - V_{T}}{\frac{V_{DD}}{2} + V_{T}})^2$ If $\frac{V_{DD}}{2} >> V_T$: $\frac{(\frac{W}{L})_p}{(\frac{W}{L})_n} = \frac{\mu_n}{\mu_p}$ ### Switching Characteristics * **Low-to-high propagation delay, $t_{pLH}$**: The time required for the output to rise to the 50% point when the input switches from low to high. * **High-to-low propagation delay, $t_{pHL}$**: The time required for the output to drop to the 50% point when the input switches from high to low. * **Propagation delay, $t_p$**: $t_p = (t_{pLH} + t_{pHL})/2$ * **Rise time, $t_{r}$**: The time required for a signal to rise from 10% to 90% of its final value. * **Fall time, $t_{f}$**: The time required for a signal to fall from 90% to 10% of its final value. ### Equivalent Circuit for Delay Calculation $C_L$: Load capacitance $i_{avg} = C_L \frac{\Delta V}{\Delta t}$ $\Delta t = C_L \frac{\Delta V}{i_{avg}}$ $t_{pHL} = C_L \frac{V_{DD}/2}{i_{avg}} = C_L \frac{V_{DD}/2}{\frac{1}{2} k_n' (\frac{W}{L})_n (V_{DD} - V_{TN})^2 (1 + \lambda V_{DD}/2)}$ $t_{pLH} = C_L \frac{V_{DD}/2}{i_{avg}} = C_L \frac{V_{DD}/2}{\frac{1}{2} k_p' (\frac{W}{L})_p (V_{DD} + V_{TP})^2 (1 + \lambda V_{DD}/2)}$ ### Power Dissipation Two components: * **Static dissipation**: Due to leakage current. * **Dynamic dissipation**: Due to switching transient current and charging and discharging of load capacitance. ### Dynamic Power Dissipation $P_{dynamic} = C_L V_{DD}^2 f$ $f$: switching frequency. * Short-circuit current occurs when both the NMOS and PMOS transistors are simultaneously ON for a short period during the switching transient. * The short-circuit power dissipation can be minimized by ensuring fast input signal waveforms, so that both transistors are not ON simultaneously for a significant duration. ### Static Power Dissipation Due to subthreshold conduction current and gate-tunneling current. ### Ratioed Logic To reduce the number of transistors. ### Pseudo-NMOS Inverter Replace PMOS pull-up with a grounded PMOS transistor. ### Pass-Transistor Logic Use NMOS transistors as switches.