Bic10503 Comp Arch Chapter 4: Input/Output PDF

BIC10503 – Comp Arch Chapter 4: Input / Output Design Issues There are wide variety of peripherals with various methods of operation. Mismatch between the data transfer rate of peripherals and the data transfer rate of memory/processor. Peripherals often use different data formats an...

BIC10503 – Comp Arch Chapter 4: Input / Output Design Issues There are wide variety of peripherals with various methods of operation. Mismatch between the data transfer rate of peripherals and the data transfer rate of memory/processor. Peripherals often use different data formats and word lengths than the computer to which they are attached. Solution Impractical to use the high-speed system bus to communicate directly with a peripheral. Thus, require an intermediate module. Called I/O Module. I/O Module Two functions: Interface to the processor and memory via the system bus or central switch. Interface to one or more peripheral devices by tailored data links. Generic Model of an I/O Module External Devices provide a means of exchanging data between the external environment and the computer. An external device attaches to the computer by a link to an I/O module. The link is used to exchange control, status, and data between the I/O module and the external device. An external device connected to an I/O module is often referred to as a peripheral device or, simply, a peripheral. External Devices Categories: Human readable : Suitable for comm. with the computer user Screen, printer, keyboard Machine readable : suitable for comm. with equipment Magnetics disk, tape system Sensors and actuators (used in a robotic application) Communication : suitable for comm. with remote devices Modem Network Interface Card (NIC) External Devices Control signals determine: the function that the device will perform, such as send data to the I/O module (INPUT or READ), accept data from the I/O module (OUTPUT or WRITE), report status, or perform some control function particular to the device (e.g., position a disk head) Status signals indicate the state of the device Block diagram of an External Device External Devices Control logic controls the device’s operation in response to direction from the I/O module. Transducer converts data from electrical to other forms of energy during output and from other forms to electrical during input. Buffer temporarily hold data being transferred between the I/O module and the external environment. Block diagram of an External Device I/O Module  Control & Timing : to coordinate the flow of traffic between internal resources and external devices.  Device Communication : This communication involves commands, status information, and data  Data Buffering : Whereas the transfer rate into and out of main memory or the processor is quite high, the rate is orders of magnitude lower for many peripheral devices and covers a wide range  Error Detection : for subsequently reporting errors to the processor. One class of errors includes mechanical and electrical malfunctions reported by the device I/O Module  CPU Communication :  Command decoding I/O module accepts commands from the processor, typically sent as signals on the control bus.  Data: Data are exchanged between the processor and the I/O module over the data bus.  Status reporting : Because peripherals are so slow, it is important to know the status of the I/O module  Address recognition : I/O module must recognize one unique address for each peripheral it controls. I/O Steps If ready, CPU checks I/O module CPU I/O module I/O module I/O module, returns requests gets data transfers device status data from device data to CPU status transfer I/O Module Block diagram of an I/O Module I/O Module Decisions Hide or reveal device properties to CPU Support multiple or single device Control device functions or leave for CPU Also O/S decisions e.g. Unix treats everything it can as a file I/O Operation Techniques Programmed Interrupt-driven Direct Memory Access (DMA) I/O Techniques I/O Techniques 4.3 Programmed I/O Programmed I/O CPU has direct control over I/O ◦ Sensing status ◦ Read/write commands ◦ Transferring data CPU waits for I/O module to complete operation Wastes CPU time Programmed I/O CPU requests I/O operation I/O module performs operation I/O module sets status bits CPU checks status bits periodically I/O module does not inform CPU directly I/O module does not interrupt CPU CPU may wait or come back later I/O Commands Issued by the processor (CPU) to the I/O Module CPU issues address Identifies a module (& device if >1 per module) CPU issues an I/O command. There are four types: Control - telling module what to do e.g. spin up disk Test - check status e.g. power? Error? Read Module transfers data via buffer from device Write Module transfers data via buffer to device I/O Instructions  Executed by the processor  With programmed I/O, there is a close correspondence between the I/O-related instructions and the I/O commands  The form of the instruction depends on the way in which external devices are addressed.  When the processor issues an I/O command, the command contains the address of the desired device.  Thus, each I/O module must interpret the address lines to determine if the command is for itself Addressing I/O Devices Under programmed I/O data transfer is very like memory access (CPU viewpoint) Each device given unique identifier CPU commands contain identifier (address) Addressing Modes Memory mapped I/O Devices and memory share an address space e.g. 4-bit address space can support 24 memory locations & I/O devices I/O looks just like memory read/write No special commands for I/O Large selection of memory access commands available Isolated I/O Separate address spaces Need I/O or memory select lines Special commands for I/O Limited set Memory Mapped and Isolated I/O 4.4 Interrupt-Driven I/O Interrupt Driven I/O Overcomes CPU waiting No repeated CPU checking of device I/O module interrupts when ready Interrupt Driven I/O Basic Operation CPU issues read command I/O module gets data from peripheral whilst CPU does other work I/O module interrupts CPU CPU requests data I/O module transfers data Simple Interrupt Processing PSW : Processor Status Word PC : Program Counter CPU Viewpoint Issue read command Do other work Check for interrupt at end of each instruction cycle If interrupted:- Save context (registers) Process interrupt Fetch data & store Changes in Memory and Registers for an interrupt Design Issues  How do you identify which device issuing the interrupt?  How do you deal with multiple interrupts?  Four general categories of techniques are in common use:  Multiple interrupt line  Software poll  Daisy chain (hardware poll)  Bus arbitration Identify Interrupting Module Different line for each module Limits number of devices Impractical to dedicate few bus line Solve : one of the other technique must be used Software poll CPU asks each module in turn Routine whose job it is to poll each I/O module to determine which module cause the interrupt Slow : time consuming Identify Interrupting Module Daisy Chain or Hardware poll All I/O modules share a common interrupt request line Interrupt Acknowledge sent down a chain Module responsible places vector on bus CPU uses vector to identify handler routine It avoids need to execute general interrupt-service routine Bus arbitration Module must claim the bus before it can raise interrupt e.g. PCI & SCSI Multiple Interrupts Each interrupt line has a priority Higher priority lines can interrupt lower priority lines Software polling: the order in which modules are polled determines their priority. Daisy Chain: the order of modules determines their priority. Bus arbitration: employ any priority scheme. 4.5 Direct Memory Access (DMA) DMA  Interrupt driven and programmed I/O require active CPU intervention ◦ Transfer rate is limited ◦ CPU is tied up  DMA is the answer  capable of mimicking the processor and, indeed, of taking over control of the system from the processor  DMA module must use the bus only when the processor does not need it, or it must force the processor to suspend operation temporarily (called cycle stealing). DMA Functions: Additional module (hardware) on system bus DMA controller takes over from CPU for I/O Typical DMA Module diagram DMA Operations CPU tells DMA controller:- Read/Write Device address Starting address of memory block for data Amount of data to be transferred CPU carries on with other work DMA controller deals with transfer DMA controller sends interrupt when finished DMA Cycle Stealing DMA controller takes over bus for a cycle Transfer of one word of data Not an interrupt CPU does not switch context CPU suspended just before it accesses bus i.e. before an operand or data fetch or a data write Slows down CPU but not as much as CPU doing transfer DMA and Interrupt Breakpoints During an Instruction Cycle Note : This is NOT an interrupt; the processor does not save a context and do something else. Rather, the processor pauses for one bus cycle. The overall effect is to cause the processor to execute more slowly. Nevertheless, DMA is far more efficient than interrupt-driven or programmed I/O. DMA Configurations  The DMA mechanism can be configured in a variety of ways:  Single-Bus  Single-Bus Integrated DMA  Alternative DMA configuration DMA Configurations Single Bus, detached DMA controller Each transfer uses bus twice I/O to DMA then DMA to memory CPU is suspended twice DMA Configurations Single bus, integrated DMA controller Controller may support >1 device Each transfer uses bus once DMA to memory CPU is suspended once DMA Configurations Separate I/O bus Bus supports all DMA enabled devices Each transfer uses bus once DMA to memory CPU is suspended once 4.6 I/O Channel and Processor I/O Channels As computer systems have evolved, there has been a pattern of increasing complexity and sophistication of individual components. I/O devices getting more sophisticated e.g. 3D graphics cards CPU instructs I/O controller to do transfer I/O controller does entire transfer Improves speed Takes load off CPU Dedicated processor is faster I/O Channel Evolutionary: More I/O function is performed without CPU involvement. CPU is increasingly relieved of I/O-related tasks, thus improving performance I/O Channel (or I/O processor) has the ability to execute I/O instructions I/O Channel Architecture  Two types.  controls multiple high-speed devices at any one time  Each device, or a small set of devices, is handled by a controller  can handle I/O with multiple devices at the same time  For low-speed devices, a byte multiplexor accepts or transmits characters as fast as possible to multiple devices Interfacing  The interface to a peripheral from an I/O module must be tailored to the nature and operation of the peripheral. parallel interface: multiple  One major characteristic of the interface is whether it is serial or parallel lines connecting the I/O module and the peripheral, and multiple bits are transferred simultaneously. e.g.: tape and disk serial interface: only one line used to transmit data, and bits must be transmitted one at a time. e.g.: printers Interfacing: I/O Modules and External Devices Point-to-Point Multipoint provides a used to support dedicated line external mass between the I/O storage devices module and the (disk and tape external device. drives) and keyboard, printer, multimedia and external devices (CD-ROMs, modem video, audio) Examples: FireWire and Infiniband. External Interconnection Standards Universal Serial Bus (USB) FireWire Serial Bus Small Computer System Interface (SCSI) Thunderbolt InfiniBand PCI Express Serial Advanced Technology Attachment (SATA) Ethernet Wi-Fi USB Widely used to connect peripherals. Multiple generations: USB 1.0 (1.5 Mbps) USB 2.0 (480 Mbps) USB 3.0 (up to 4 Gbps) USB 3.1 (up to 9.7 Gbps) IEEE 1394 FireWire High performance serial bus Fast Low cost Easy to implement Also being used in digital cameras, VCRs and TV FireWire Configuration Daisy chain Up to 63 devices on single port Really 64 of which one is the interface itself Up to 1022 buses can be connected with bridges Automatic configuration No bus terminators May be tree structure Simple FireWire Configuration FireWire 3 Layer Stack Physical Transmission medium, electrical and signaling characteristics Link Transmission of data in packets Transaction Request-response protocol FireWire Protocol Stack FireWire - Physical Layer Data rates from 25 to 400Mbps Two forms of arbitration Based on tree structure Root acts as arbiter First come first served Natural priority controls simultaneous requests i.e. who is nearest to root Fair arbitration Urgent arbitration FireWire - Link Layer Two transmission types Asynchronous Variable amount of data and several bytes of transaction data transferred as a packet To explicit address Acknowledgement returned Isochronous Variable amount of data in sequence of fixed size packets at regular intervals Simplified addressing No acknowledgement InfiniBand I/O specification aimed at high end servers Merger of Future I/O (Cisco, HP, Compaq, IBM) and Next Generation I/O (Intel) Version 1 released early 2001 Architecture and spec. for data flow between processor and intelligent I/O devices Intended to replace PCI in servers Increased capacity, expandability, flexibility InfiniBand in action InfiniBand Architecture  Remote storage, networking and connection between servers  Attach servers, remote storage, network devices to central fabric of switches and links  Greater server density  Scalable data centre  Independent nodes added as required  I/O distance from server up to ◦ 17m using copper ◦ 300m multimode fibre optic ◦ 10km single mode fibre  Up to 30Gbps InfiniBand Switch Fabric InfiniBand Operations 16 logical channels (virtual lanes) per physical link One lane for management, rest for data Data in stream of packets Virtual lane dedicated temporarily to end to end transfer Switch maps traffic from incoming to outgoing lane Summary The computer system’s I/O architecture is its interface to the outside world. This architecture provides a systematic means of controlling interaction with the outside world and provides the operating system with the information it needs to manage I/O activity effectively. The are three principal I/O techniques: programmed I/O, in which I/O occurs under the direct and continuous control of the program requesting the I/O operation; interrupt-driven I/O, in which a program issues an I/O command and then continues to execute, until it is interrupted by the I/O hardware to signal the end of the I/O operation; and direct memory access (DMA), in which a specialized I/O processor takes over control of an I/O operation to move a large block of data. Thank You Q&A