04_CPU and Memory.pptx

System Software and Computing Concepts CT123-3-1Ver: VDE CPU and Memory  Topics we will cover CPU Components The Concept of Registers The Memory Unit Fetch-Execute Cycle Buses...

System Software and Computing Concepts CT123-3-1Ver: VDE CPU and Memory  Topics we will cover CPU Components The Concept of Registers The Memory Unit Fetch-Execute Cycle Buses Instructions and Word Formats Module Code & Module Title Slide Title SLIDE 2  Learning Outcomes At the end of this section, YOU should be able to: Describe the structure, components and functions of a computer system Module Code & Module Title Slide Title SLIDE 3  Key Terms Module Code & Module Title Slide Title SLIDE 4  CPU: Major Components ALU (arithmetic logic unit) – Performs calculations and comparisons CU (control unit) – Performs fetch/execute cycle Accesses program instructions and issues commands to the ALU Moves data to and from CPU registers and other hardware components – Subcomponents: Memory management unit: supervises fetching instructions and data from memory I/O Interface: sometimes combined with memory management unit as Bus Interface Unit Module Code & Module Title Slide Title SLIDE 5  System Block Diagram Module Code & Module Title Slide Title SLIDE 6  The Little Man Computer Module Code & Module Title Slide Title SLIDE 7  Concept of Registers Small, permanent storage locations within the CPU used for a particular purpose Manipulated directly by the Control Unit Wired for specific function Size in bits or bytes (not in MB like memory) Can hold data, an address or an instruction Module Code & Module Title Slide Title SLIDE 8  Registers Use of Registers – Scratchpad for currently executing program Holds data needed quickly or frequently – Stores information about status of CPU and currently executing program Address of next program instruction Signals from external devices General Purpose Registers – User-visible registers – Hold intermediate results or data values, e.g., loop counters – Equivalent to LMC’s calculator – Typically several dozen in current CPUs Module Code & Module Title Slide Title SLIDE 9  Special-Purpose Registers Program Count Register (PC) – Also called instruction pointer Instruction Register (IR) – Stores instruction fetched from memory Memory Address Register (MAR) Memory Data Register (MDR) Status Registers – Status of CPU and currently executing program – Flags (one bit Boolean variable) to track condition like arithmetic carry and overflow, power failure, internal computer error Module Code & Module Title Slide Title SLIDE 10  Register Operations Stores values from other locations (registers and memory) Addition and subtraction Shift or rotate data Test contents for conditions such as zero or positive Module Code & Module Title Slide Title SLIDE 11  Operation of Memory Each memory location has a unique address Address from an instruction is copied to the MAR which finds the location in memory CPU determines if it is a store or retrieval Transfer takes place between the MDR and memory MDR is a two way register Module Code & Module Title Slide Title SLIDE 12  Relationship between MAR, MDR and Memory Addres Data s Module Code & Module Title Slide Title SLIDE 13  MAR-MDR Example Module Code & Module Title Slide Title SLIDE 14  Visual Analogy of Memory Module Code & Module Title Slide Title SLIDE 15  Individual Memory Cell Module Code & Module Title Slide Title SLIDE 16  Memory Capacity Determined by two factors 1. Number of bits in the MAR LMC = 100 (00 to 99) 2K where K = width of the register in bits 2. Size of the address portion of the instruction 4 bits allows 16 locations 8 bits allows 256 locations 32 bits allows 4,294,967,296 or 4 GB Module Code & Module Title Slide Title SLIDE 17  RAM: Random Access Memory DRAM (Dynamic RAM) – Most common, cheap, less electrical power, less heat, smaller space – Volatile: must be refreshed (recharged with power) 1000’s of times each second SRAM (static RAM) – Faster and more expensive than DRAM – Volatile – Small amounts are often used in cache memory for high-speed memory access Module Code & Module Title Slide Title SLIDE 18  Nonvolatile Memory ROM – Read-only Memory – Holds software that is not expected to change over the life of the system EEPROM – Electrically Erasable Programmable ROM Flash Memory – Faster than disks but more expensive – Uses hot carrier injection to store bits of data – Slow rewrite time compared to RAM – Useful for nonvolatile portable computer storage Module Code & Module Title Slide Title SLIDE 19  Fetch-Execute Cycle Two-cycle process because both instructions and data are in memory Fetch – Decode or find instruction, load from memory into register and signal ALU Execute – Performs operation that instruction requires – Move/transform data Module Code & Module Title Slide Title SLIDE 20  LMC vs. CPU Fetch and Execute Cycle Module Code & Module Title Slide Title SLIDE 21 Load Fetch/Execute Cycle 1. PC  MAR Transfer the address from the PC to the MAR 2. MDR  IR Transfer the instruction to the IR 3. IR[address]  MAR Address portion of the instruction loaded in MAR 4. MDR  A Actual data copied into the accumulator 5. PC + 1  PC Program Counter incremented Module Code & Module Title Slide Title SLIDE 22 Store Fetch/Execute Cycle 1. PC  MAR Transfer the address from the PC to the MAR 2. MDR  IR Transfer the instruction to the IR 3. IR[address]  MAR Address portion of the instruction loaded in MAR 4. A  MDR* Accumulator copies data into MDR 5. PC + 1  PC Program Counter incremented *Notice how Step #4 differs for LOAD and STORE Module Code & Module Title Slide Title SLIDE 23 ADD Fetch/Execute Cycle 1. PC  MAR Transfer the address from the PC to the MAR 2. MDR  IR Transfer the instruction to the IR 3. IR[address]  MAR Address portion of the instruction loaded in MAR 4. A + MDR  A Contents of MDR added to contents of accumulator 5. PC + 1  PC Program Counter incremented Module Code & Module Title Slide Title SLIDE 24  LMC Fetch/Execute SUBTRACT IN OUT HALT PC  MAR PC  MAR PC  MAR PC  MAR MDR  IR MDR  IR MDR  IR MDR  IR IR[addr]  MAR IOR  A A  IOR A – MDR  A PC + 1  PC PC + 1  PC PC + 1  PC BRANCH BRANCH on Condition PC  MAR PC  MAR MDR  IR MDR  IR IR[addr]  PC If condition false: PC + 1  PC If condition true: IR[addr]  PC Module Code & Module Title Slide Title SLIDE 25  Bus The physical connection that makes it possible to transfer data from one location in the computer system to another Group of electrical or optical conductors for carrying signals from one location to another – Wires or conductors printed on a circuit board – Line: each conductor in the bus 4 kinds of signals 1. Data 2. Addressing 3. Control signals Module Code & Module Title Slide Title SLIDE 26  Bus Characteristics Number of separate conductors Data width in bits carried simultaneously Addressing capacity Lines on the bus are for a single type of signal or shared Throughput - data transfer rate in bits per second Distance between two endpoints Number and type of attachments supported Type of control required Defined purpose Features and capabilities Module Code & Module Title Slide Title SLIDE 27  Bus Categorizations Parallel vs. serial buses Direction of transmission – Simplex – unidirectional – Half duplex – bidirectional, one direction at a time – Full duplex – bidirectional simultaneously Method of interconnection – Point-to-point – single source to single destination Cables – point-to-point buses that connect to an external device – Multipoint bus – also broadcast bus or multidrop bus Connect multiple points to one another Module Code & Module Title Slide Title SLIDE 28  Parallel vs. Serial Buses Parallel – High throughput because all bits of a word are transmitted simultaneously – Expensive and require a lot of space – Subject to radio-generated electrical interference which limits their speed and length – Generally used for short distances such as CPU buses and on computer motherboards Serial – 1 bit transmitted at a time – Single data line pair and a few control lines – For many applications, throughput is higher than for parallel because of the lack of electrical interference Module Code & Module Title Slide Title SLIDE 29  Point-to-point vs. Multipoint Plug- in Broadcas device t bus Example: Ethernet Shared among multiple devices Module Code & Module Title Slide Title SLIDE 30  Classification of Instructions Data Movement (load, store) – Most common, greatest flexibility – Involve memory and registers – What’s this size of a word ? 16? 32? 64 bits? Arithmetic – Operators + - / * ^ – Integers and floating point Boolean Logic – Often includes at least AND, XOR, and NOT Single operand manipulation instructions – Negating, decrementing, incrementing, set to 0 Module Code & Module Title Slide Title SLIDE 31 More Instruction Classifications Bit manipulation instructions – Flags to test for conditions Shift and rotate Program control Stack instructions Multiple data instructions I/O and machine control Module Code & Module Title Slide Title SLIDE 32  Register Shifts and Rotates Module Code & Module Title Slide Title SLIDE 33 Program Control Instructions Program control – Jump and branch – Subroutine call and return Module Code & Module Title Slide Title SLIDE 34 Stack Instructions Stack instructions – LIFO method for organizing information – Items removed in the reverse order from that in which they are added Push Pop Module Code & Module Title Slide Title SLIDE 35  Block of Memory as a Stack Module Code & Module Title Slide Title SLIDE 36  Multiple Data Instructions Perform a single operation on multiple pieces of data simultaneously – SIMD: Single Instruction, Multiple Data – Commonly used in multimedia, vector and array processing applications Module Code & Module Title Slide Title SLIDE 37  Multiple Data Instructions OPCODE: task Source OPERAND(s) Result OPERAND – Location of data (register, memory) Addresses Explicit: included in instruction Implicit: default assumed Source Result OPCODE OPERAND OPERAND Module Code & Module Title Slide Title SLIDE 38 Instruction Format Machine-specific template that specifies – Length of the op code – Number of operands – Length of operands Simple 32-bit Instruction Format Module Code & Module Title Slide Title SLIDE 39  Instructions Instruction – Direction given to a computer – Causes electrical or optical signals to be sent through specific circuits for processing Instruction set – Design defines functions performed by the processor – Differentiates computer architecture by the Number of instructions Complexity of operations performed by individual instructions Data types supported Format (layout, fixed vs. variable length) Use of registers Addressing (size, modes) Module Code & Module Title Slide Title SLIDE 40  Instruction Word Size Fixed vs. variable size – Pipelining has mostly eliminated variable instruction size architectures Most current architectures use 32-bit or 64-bit words Addressing Modes – Direct Mode used by the LMC – Register Deferred – Also immediate, indirect, indexed Module Code & Module Title Slide Title SLIDE 41 Instruction Format Examples Module Code & Module Title Slide Title SLIDE 42  Quick Review Questions The instruction cycle is divided into two phases. Name each phase. The first phase is the same for every instruction. What is the purpose of the first phase that makes this true? What are the criteria that define a von Neumann architecture? How does the addition of two numbers illustrate each of the criteria? What is the difference between volatile and nonvolatile memory? Is RAM volatile or nonvolatile? Is ROM volatile or nonvolatile? Registers perform a very important role in the fetch-execute cycle. What is the function of registers in the fetch-execute instruction cycle? Explain each of the fetch part of the fetch-execute cycle. At the end of the fetch operation, what is the status of the instruction? Specifically, what has the fetch operation achieved that prepares the instruction for execution? Explain the similarity between this operation and the corresponding operation performed steps performed by the Little Man. Module Code & Module Title Slide Title SLIDE 43  Summary The workings of the computer can be simulated by a simple model. The Little Man Computer model consists of a Little Man in a mailroom with mailboxes, a calculator, and a counter. Input and output baskets provide communication to the outside world. The Little Man Computer meets all the qualifications of a von Neumann computer architecture. The Little Man performs work by following simple instructions, which are described by three- digit numbers. The first digit specifies an operation. The last two digits are used for various purposes, but most commonly to point to an address. The instructions provide operations that can move data between the mail slots and the calculator, move data between the calculator and the input and output baskets, perform addition and subtraction, and allow the Little Man to stop working. There are also instructions that cause the Little Man to change the order in which instructions are executed, either unconditionally or based on the value in the calculator. Module Code & Module Title Slide Title SLIDE 44  END Q&A Module Code & Module Title Slide Title SLIDE 45  Next CPU & Memory Module Code & Module Title Slide Title SLIDE 46