Moore's Law: The Journey Ahead PDF

SPECIAL SEC TION T RA N S I S T O R S DEVICE TECHNOLOGY Moore’s law: The journey ahead High-performance electronics will focus on increasing the rate of computation By Mark S. Lundstrom and off current ratio to allow practical opera-...

SPECIAL SEC TION T RA N S I S T O R S DEVICE TECHNOLOGY Moore’s law: The journey ahead High-performance electronics will focus on increasing the rate of computation By Mark S. Lundstrom and off current ratio to allow practical opera- The number of transistors on a chip Muhammad A. Alam tion and suppress leakage current to reduce is still increasing, but the rate of scaling wasted power. In 2003, strained silicon has slowed because smaller transistors T he transistor was invented 75 years was introduced as channel material, and do not function very well. Specifically, the ago, and the integrated circuit (IC) it increased the on-current by increasing length of the channel (the region between soon thereafter. The progress in the velocity of electrons (3), and in 2004, the source and drain electrode where the making transistors smaller also led gate insulators with a high dielectric con- gate acts as a switch) is now ~10 nm. At to them becoming cheaper, which stant decreased the off-state gate-leakage shorter channel lengths, excessive quan- was famously noted as Moore’s law current. In 2011, the FinFET, a nonplanar tum-mechanical tunneling degrades tran- (1). Today’s sophisticated processor chips transistor structure that increases the elec- sistor action. Key performance metrics, contain more than 100 billion transistors, trostatic control of the energy barrier by such as on-current (which should be high but the pace of downsizing (“scaling”) the gate electrode (and thereby improves for high-speed operation), off-current has slowed and it is no longer the only or the on-off current ratio), was introduced (which should be low to minimize standby even main design goal for improv- power), and power supply voltage ing performance in particular ap- (which should be low to minimize plications. How can Moore’s law Three platforms forward the power consumed), all degrade continue on a path forward? New Two-dimensional (2D) nanoelectonics, three-dimensional (3D) terascale simultaneously. Silicon MOSFETS approaches include three-dimen- integration, and functional integration can all extend Moore’s law, but all are now about as small as they can sional (3D) integration that will face substantial challenges and fundamental limits. get, and the 2D chips are about as focus on increasing the rate of in- large as they can be made, so new formation processing, rather than Platforms Challenges Limits ways to advance performance must on increasing the density of tran- be found. 2D nanoelectronics Heat sistors on a chip. dissipation Performance is being enhanced Although Moore’s law predicted Although other design challenges Process Electron by moving from general-purpose, a rate for the decrease in cost per can be met, smaller transistors, even integration tunneling “commodity chips” to ones that ones enabled by advanced surround- transistor, it is popularly viewed gate design, will eventually hit the Lithography accelerate specific functions. For in terms of transistor size, which electron tunneling limit. example, hardware acceleration for two-dimensional (2D) chip ar- offloads specific tasks to spe- rays translates into an areal size or 3D terascale integration Process cialized chips such as graphics “footprint.” During the last 75 years, integration processing units or an application- Transistor count can increase 3D design Heat as the footprint has decreased from through 3D monolithic integration dissipation specific IC. Companies such as Ap- micrometer to nanometer scales, or stacking of logic, memory, and Reliability ple now design their own chips to issues with implementing new fab- power chips. The approach, however, Lab-to-Fab meet their specific requirements, rication technologies have raised faces several design challenges and as will all of the major automobile heat dissipation limits. concerns several times about the manufacturers. Computing is the “end of Moore’s Law.” Twenty years Functional integration Application- limiting factor for machine learn- ago, a pessimistic outlook pre- specific design ing, and companies such as Google vailed regarding the development Integrating intelligent sensing, Unknown now design their own artificial in- Developing actuation, and data analytics sensors and of several difficult technologies for would improve functional perform- telligence (AI) accelerator chips. edge analytics scaling to continue. In this con- ance by sending information Custom chip designs can increase text, one of the authors (M.S.L.) instead of raw data. performance by orders of magni- predicted that instead of slowing tude, but just as the cost of chip down, the scaling of metal-oxide-semicon- in commercial ICs. Gate all-around transis- manufacturing facilities (“fabs”) has mul- ductor field-effect transistors (MOSFETs) tors that further improve the electrostatic tiplied (from ~$1 billion in 2000 to ~ $20 below the so-called 65-nm node, which was control of the gate are now in development billion for a leading-edge fab), so has the state-of-the-art in 2003, would continue (4). The size of transistors that can be fabri- cost of leading-edge design. The design of a unabated for at least a decade before the cated is limited by patterning and etching. leading-edge chip can cost $0.5 billion and scaling limit was reached (2). Patterning is done by a process known as require a team of ~1000 engineers. Lower- Scaling indeed continued from about photolithography, in which a photoreactive ing the cost of leading-edge, custom-chip GRAPHIC: K. HOLOSKI/SCIENCE 100 million transistors per chip in 2003 to polymer creates a mask on the chip for etch- design (possibly by using machine learning as many as 100 billion transistors per chip ing steps. The minimum size of the pattern techniques) will be a key challenge for the today. One approach was to improve the on- is determined by the wavelength of the light next era of electronics. used. The recent emergence of extreme ul- Continued progress will also require traviolet lithography (EUV) made it possi- advances in the underlying technology. School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-1971, USA. ble for Moore’s law to continue beyond the Despite the sharp increase in the number Email: [email protected] 7-nm node (5). of transistors on chips (both by decreasing 722 18 NOVEMBER 2022 VOL 378 ISSUE 6621 science.org SCIENCE their size and increasing the 2D chip area), developed. Stacking already-processed 2D experimental loops that maximize learning until recently one aspect of the design had chips to achieve 3D systems has its own are needed. remained largely unchanged. Individual set of material and processing challenges, Thermal issues will define the limits of chips are packaged and combined with such as maintaining interconnect align- 3D terascale integration, just as tunnel- other chips and other components (such ment over distances of ~1 to 5 mm. Hetero- ing limits have stymied 2D scaling. This as inductors) laterally on printed circuit geneous integration of components such as requirement need not herald an end of boards. Sending signals on- and off-chip Si high- and low-voltage logic and memory Moore’s law. The goal of computing is not increases delays and power consumption. transistors, and compound semiconduc- operations per second but information per An emerging design theme is to exploit tor-based power and high-frequency tran- second. In that regard, biology offers a the third (vertical) dimension to enable sistors, presents another set of complex guide. Human senses process information terascale integration (TSI), with trillions integration challenges. locally before forwarding it to the brain. of transistors integrated into monolithic or Transistors generate heat when they op- Empowering the sensors at the edge that stacked chips and terabits per second per erate, and removing the heat is a serious interfaces the analog world, supported by millimeter communication speed for elec- issue in electronics today (7, 10). Indeed, local memory and data processing (edge trical or optical interconnections (“per mil- thermal cross-talk among logic, memory, analytics), could prevent the data deluge limeter” refers to the communication link power transistors, and inductors in a het- from overwhelming the computer. distance between the chips). For example, a erogeneous IC creates unprecedented de- Electronics is at an inflection point. For 3D NAND flash memory (which is based on sign challenges. New ways to remove heat, 75 years, it has been possible to make tran- NAND logic gates and retains its states with perhaps mimicking the thermoregulation sistors smaller, but that will not be the driv- the power off ) can have nearly 200 layers of organisms, and thermally aware design ing force for progress in the decades ahead. of devices and half a trillion memory tran- will be critical when trillions of transistors If Moore’s law is understood to refer to the sistors (6). Emerging logic transistors with are placed in close proximity. increasing number of transistors per inte- new channel materials (such as transition The reliability of electronic systems must grated system (not necessarily per chip), metal dichalcogenides and indium oxide) be guaranteed for a minimum time, typi- then the end of Moore’s law is not in sight that can be processed at low temperatures cally 10 years, but decades for some applica- (see the figure). The increasing number of and embedded within the interconnect tions. Ensuring a failure rate between 1 and transistors will not come by making them stacks offer further opportunities. 10 parts per million for ICs with 100 billion smaller, but by stacking them vertically or The third dimension also opens up the transistors each requires predicting the reli- combining them laterally in sophisticated possibility of vertical heterogeneous in- ability of quintillion (~1018) transistors. In packages, and eventually in monolithic 3D tegration of logic, memory, and power practice, reliability is determined through chips and adding functionality. transistors. With “through-Si vias,” metal short-term accelerated testing of no more Shifting from nanoelectronics (focused wires that connect vertically from the chip, than a few thousand transistors. Thus, the on reducing the transistor dimension) to already-processed chips can be stacked to reliability physics of the wear-out and cata- terascale electronics (driven by increas- put them in close physical proximity to strophic failure modes of these new systems ing transistor count and related function- minimize signal delays and reduce power need to be understood with unprecedented ality) defines the paradigm shift and core consumption (7). Vertically stacked logic precision. When so many devices are inter- research challenges of the future. It will and memory chips also enable new com- connected and placed in close proximity, require fundamental advances in materi- puting paradigms, such as “compute-in- new phenomena will emerge, and these als, devices, processing, and the design and memory.” Monolithic 3D ICs would consist must be managed or exploited. manufacture of the most complex systems of layers of active devices, such as 2D logic Future terascale systems will be funda- humans have ever built. Someday the elec- transistors, magnetoresistive and resistive mentally different from today’s gigascale trical tunneling and thermal bottleneck will random-access memories, and ferroelectric systems in that understanding the building define the limits of 3D integration. Until FETs, along with the metal lines that inter- blocks of a system do not inform how these then, Moore’s law will likely continue as re- connect them (8). blocks interact and lead to new phenom- searchers address the challenges of these ex- Recent packaging innovations, such as ena (11). Chip design is already complex traordinarily complex electronic systems. j silicon-interposer and multi-die silicon and expensive, but algorithms or tools to REF ERENCES AND NOTES bridges, inserted between the 3D chips place devices for 3D design and routing the 1. G. E. Moore, Electronics (Basel) no. 8 (19 April 1965) and the substrate, create denser lateral interconnections among them are not yet (1965). interconnection and faster communica- available. These design tools must model 2. M. Lundstrom, Science 299, 210 (2003). tion among the chips. Advanced packaging the complexity of the process and package 3. K. Mistry et al., in IEEE International Electron Devices brings together logic, memory, power man- integration, thermal cross-talk among 3D Meeting, pp. 247250 (2007). 4. D. Jang et al., IEEE Trans. Electron Dev. 64, 2707 (2017). agement, communications, and photon- ICs, and operation-specific variability and 5. WIRED, “The $150 million machine keeping Moore’s law ics through side-by-side integration. The reliability of the packaged system. alive,” 30 August 2021; https://www.wired.com/story/ proximity of integration now rivals that in When new materials and processing asml-extreme-ultraviolet-lithography-chips-moores- stacked and monolithic 3D ICs (8, 9). techniques are developed in research, they law/. 6. A. Goda, Electronics 10, 3156 (2021). Monolithic 3D integration will require must be translated to large-scale manufac- 7. R. W. Keyes, Proc. IEEE 60, 225 (1972). that the growth or deposition steps do not turing. Translating advances achieved with 8. S. Iyer, IEEE Trans. Compon. Packaging Manuf. Technol. 6, affect the already-processed layers. For ex- research-grade equipment to large-scale 973 (2016). ample, the transistors embedded within manufacturing with different and more so- 9. C. H. Douglas et al., in 2021 IEEE International Electron Devices Meeting, pp. 3–7. the interconnect stack must be deposited phisticated state-of-the-art manufacturing 10. M. A. Alam et al., IEEE Trans. Electron Dev. 66, 4556 at a low-enough temperature not to disturb equipment presents a serious “lab to fab” (2019). the dopant profiles of the Si transistors un- challenge. The research community will 11. P. W. Anderson, Science 177, 393 (1972). derneath. The needed materials are often need access to advanced processing facili- incompatible unless special processes are ties, and short “conceive-conduct-analyze” 10.1126/science.ade2191 SCIENCE science.org 18 NOVEMBER 2022 VOL 378 ISSUE 6621 723