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Define the concept of a memory consistency model in the context of a shared-memory multiprocessor.
Define the concept of a memory consistency model in the context of a shared-memory multiprocessor.
deals with how accesses (loads and stores) to any memory address are ordered with respect to one another as seen by all processors. Note that this is not a problem that is covered by the cache coherence protocol, since a cache coherence protocol only deals with how accesses to a single memory block address are ordered. Accesses to different addresses are not the concern of cache coherence protocols. In fact, unlike the cache coherence problem that only occurs for systems with caches, the memory consistency problem exists on systems with and without caches, although caches may exacerbate it.
Define Sequential Consistency.
Define Sequential Consistency.
A multiprocessor is sequentially consistent if the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operations of each individual processor occur in this sequence in the order specified by its program.
basically if you combined all the executed instructions of all the processors, it would look like they were all just taking turns executing instructions. In this mega list of instructions, each processors own contributions must match the same order as it's own set of instructions.
Mark the answer as true if the outcome (a,b) could be produced and be Sequentially Consistent.
P0:
S1: a = 1;
S2: b = 1;
P1:
S3: ... = b;
S4: ... =a;
Mark the answer as true if the outcome (a,b) could be produced and be Sequentially Consistent. P0: S1: a = 1; S2: b = 1;
P1: S3: ... = b; S4: ... =a;
For this problem:
P0:
S1: a = 1;
S2: b = 1;
P1:
S3: ... = b;
S4: ... =a;
Give a possible ordering for the following outcomes of a,b:
00
01
10
11
For this problem: P0: S1: a = 1; S2: b = 1;
P1: S3: ... = b; S4: ... =a;
Give a possible ordering for the following outcomes of a,b: 00 01 10 11
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Define Load Forwarding and Load Bypassing.
Define Load Forwarding and Load Bypassing.
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What 2 rules exist for weak consistency.
What 2 rules exist for weak consistency.
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Explain Release Consistency.
Explain Release Consistency.
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Do problem 1 in 9.5 exercises in text. Put True if correct, false if answers were wrong.
Do problem 1 in 9.5 exercises in text. Put True if correct, false if answers were wrong.
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Do problem 3 in 9.5 exercises in text. Put True if correct, false if answers were wrong.
Do problem 3 in 9.5 exercises in text. Put True if correct, false if answers were wrong.
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Do problem 4 in 9.5 exercises in text. Put True if correct, false if answers were wrong.
Do problem 4 in 9.5 exercises in text. Put True if correct, false if answers were wrong.
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Do Problem 3 in HW2. Put True if you get answers correct, false otherwise.
Do Problem 3 in HW2. Put True if you get answers correct, false otherwise.
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