Memory Consistency
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Define the concept of a memory consistency model in the context of a shared-memory multiprocessor.

deals with how accesses (loads and stores) to any memory address are ordered with respect to one another as seen by all processors. Note that this is not a problem that is covered by the cache coherence protocol, since a cache coherence protocol only deals with how accesses to a single memory block address are ordered. Accesses to different addresses are not the concern of cache coherence protocols. In fact, unlike the cache coherence problem that only occurs for systems with caches, the memory consistency problem exists on systems with and without caches, although caches may exacerbate it.

Define Sequential Consistency.

A multiprocessor is sequentially consistent if the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operations of each individual processor occur in this sequence in the order specified by its program.

basically if you combined all the executed instructions of all the processors, it would look like they were all just taking turns executing instructions. In this mega list of instructions, each processors own contributions must match the same order as it's own set of instructions.

Mark the answer as true if the outcome (a,b) could be produced and be Sequentially Consistent. P0: S1: a = 1; S2: b = 1;

P1: S3: ... = b; S4: ... =a;

  • 00 (correct)
  • 01
  • 10 (correct)
  • 11 (correct)
  • For this problem: P0: S1: a = 1; S2: b = 1;

    P1: S3: ... = b; S4: ... =a;

    Give a possible ordering for the following outcomes of a,b: 00 01 10 11

    <p>00: S3, S4, S1, S2 01: (S2, S3, S4, S1),(S2,S4,S1,S3), (S4,S1,S2,S3) 10: S1,S3,S4,S2 11: S1,S2,S3,S4</p> Signup and view all the answers

    Define Load Forwarding and Load Bypassing.

    <p>Load Forwarding: Let's say we check the store buffer, and we see a store to the address. And later we are loading the address. Since the value is in the store buffer, and has not been committed to the cache, we can just go ahead and get the value from the store buffer and not the cache. Load Bypass: If we have a load that is loading from an address that is not being stored (as seen by the stores in the store buffer). We check all the stores in the store buffer for the address we are trying to load, then we can go ahead and load before we do the stores.</p> Signup and view all the answers

    What 2 rules exist for weak consistency.

    <ol> <li>Before synchronization operation can be issued to memory, all previous memory ops must be performed.</li> <li>No later memory ops can be issued to memory until synchronization operation is performed</li> </ol> Signup and view all the answers

    Explain Release Consistency.

    <p>There are two different kinds of things when doing synchronization. There is: Release (like unlock): The data that was written at a previous time is now available for it to be consumed by other threads. Acquire (like lock): Now time to consume the data safely.</p> <p>Each of these have different reordering requirements. If marked as release, any prior memory ops have to finish. We can move later things to before this, but not earlier things to after. Acquire is the other way around, we can move thing after this, but not later things to before.</p> Signup and view all the answers

    Do problem 1 in 9.5 exercises in text. Put True if correct, false if answers were wrong.

    <p>True</p> Signup and view all the answers

    Do problem 3 in 9.5 exercises in text. Put True if correct, false if answers were wrong.

    <p>True</p> Signup and view all the answers

    Do problem 4 in 9.5 exercises in text. Put True if correct, false if answers were wrong.

    <p>True</p> Signup and view all the answers

    Do Problem 3 in HW2. Put True if you get answers correct, false otherwise.

    <p>True</p> Signup and view all the answers

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