Virtual Memory and RAM

Virtual Memory

• Applications interact with the operating system through abstractions like processes, file systems, and virtual memory.
• The operating system manages hardware resources such as the CPU, disk, and RAM.

Random-Access Memory (RAM) Features

• RAM is commonly packaged as a chip.
• The basic storage unit in RAM is a cell, which stores one bit.
• Multiple RAM chips combine to form system memory.

Static RAM (SRAM)

• Each SRAM cell stores a bit using a four or six-transistor circuit.
• SRAM retains data indefinitely while powered.
• SRAM is resistant to electrical noise and radiation.
• SRAM is faster but more expensive than DRAM.

Dynamic RAM (DRAM)

• Each DRAM cell stores a bit using a capacitor, accessed by one transistor.
• DRAM requires periodic refreshing of its value every 10-100 ms.
• DRAM is more sensitive to disturbances than SRAM.
• DRAM is slower but cheaper than SRAM.

SRAM vs DRAM Summary

• SRAM cells use 4 to 6 transistors, while DRAM cells use 1 transistor.
• SRAM has an access time of 1X, whereas DRAM has an access time of 10X.
• SRAM does not need refreshing, but DRAM does.
• SRAM may not need EDC, but DRAM does.
• SRAM is 100 times more expensive than DRAM.
• SRAM applications include cache memories.
• DRAM applications include main memories and frame buffers.

Nonvolatile Memories (NVMs)

• DRAM and SRAM are volatile, losing data without power.
• NVMs retain data even without power.
• Read-only memory(ROM) is programmed during production.
• Programmable ROM (PROM) can be programmed once.
• Eraseable PROM (EPROM) can be bulk erased using UV or X-Ray.
• Electrically eraseable PROM (EEPROM) can be erased electronically and Flash memory, EEPROMs with partial (sector) erase capability, wear out after about 100,000 erasures.
• Phase Change Memories (PCMs) wear out as well.
• Many new NVMs are emerging at various development stages.

NVM Uses

• Firmware programs are stored in ROM for BIOS, disk controllers, network cards, graphics accelerators, and security subsystems.
• Solid state disks replace rotating disks in devices like thumb drives, smartphones, tablets, and laptops.
• NVMs are used in high-end system caches.
• Universal memory is expected to replace both DRAM and disk drives.

The CPU-Memory Gap

• The speed disparity between DRAM, disk, and CPU is increasing.
• Locality is essential for bridging the CPU-Memory gap.

Locality of Reference

• Programs tend to access data and instructions with addresses near or equal to those recently used.
• Temporal locality refers to the tendency to reuse recently accessed items.
• Spatial locality refers to the tendency to access items with nearby addresses at close times.

Locality Example: Data References

• Accessing array elements in succession exhibits spatial locality.
• Repeatedly referencing a variable exhibits temporal locality.

Locality Example: Instruction References

• Executing instructions in sequence exhibits spatial locality.
• Cycling through a loop repeatedly exhibits temporal locality.

Qualitative Estimates of Locality

• Identifying a code's locality is essential for professional programmers.

Memory Hierarchies

• Properties of hardware and software include the cost per byte of fast storage technologies, CPU and main memory speed disparity and programs exhibiting good locality.
• These properties are complementary, for an approach to organizing memory and storage systems known as a memory hierarchy.

Memory Hierarchy: Caching

• Caching is used in the memory hierarchy.

Memory Hierarchy: Example

• CPU registers hold words retrieved from L1 cache.
• L1 cache holds cache lines from L2 cache (SRAM).
• L2 cache holds cache lines from main memory (DRAM).
• Main memory holds disk blocks from local disks.
• Local disks hold files from remote network servers.

Memory Hierarchy

• A smaller, faster storage device acting as a staging area for a subset of data in a larger, slower device is cache.
• Each layer of a memory hierarchy caches the layer below.
• Memory hierarchies work due to locality, so hit rate is significant although it’s smaller and storage can be slower at level k+1.
• The memory hierarchy allows programs to process data at the rate of fast storage near the top.

Cache Concepts

• Smaller, faster memory caches a subset of the blocks.
• Data is copied in block-sized transfer units.
• Larger, slower memory is viewed as partitioned into blocks.
• When data is needed and found in the cache, it is a cache hit.
• When data is not in the cache, it is a cache miss.
• On a miss, the block is fetched from memory and stored in the cache.

Cache Concepts: Miss

• Placement policy determines where the block is stored.
• Replacement policy determines which block is evicted (victim).

Types of Cache Misses

• Cold (compulsory) miss occurs when the cache is empty.
• Conflict miss occurs when multiple data objects map to the same level k block.
• Capacity miss occurs when the set of active cache blocks (working set) is larger than the cache.

Multiprogramming

• Overlap I/O and CPU of multiple jobs.
• Share physical memory across multiple processes.

Virtual Addresses

• Virtual addresses are used to manage the memory of processes.
• Instructions executed by the CPU issue virtual addresses.
• Virtual addresses are independent of the actual physical location.
• The OS determines the location of data in physical memory.
• Hardware translates virtual addresses into physical addresses, also the process's virtual address space is the set of virtual addresses.

Virtual Addresses: Translation

• The translation from virtual to physical addresses requires hardware support and OS management algorithms.
• Protection is needed to restrict which addresses jobs can use.
• Fast translation, lookups need to be fast and Updating memory hardware needs to be on context switch.

Fixed Partitions: Physical Memory

• Physical memory is divided into fixed-size partitions.
• Each partition has the same allocated memory.
• The base register is loaded by the OS when switching to a process.
• Physical address calculation= Virtual address + base register

Fixed Partition Advantages

• Easy to implement, as base register is the one requirement
• Need to verify that offset is less than fixed partition size.
• Enables fast context switch.

Fixed Partition Problems

• Internal fragmentation: memory in a partition not used by a process cannot be available to other processes.
• Partition size: one size does not fit all (very large processes?).

Variable Partitions

• Natural extension - physical memory is broken up into variable sized partitions
• Hardware requirements: base register and limit register
• Physical address = virtual address + base register
• The limit register is a fault if (virtual address > limit).

Variable Partition Advantages

• No internal fragmentation because just enough is allocated for the process.

Variable Partition Problems

• External fragmentation job loading and unloading produces empty holes scattered throughout memory.

Memory Segmentation

• It supports segmentation of memory into logically related units such as modules, procedures, stack, data and files, Units of memory from user’s perspective.
• Segments support for both variable sized partitions = 1 segment/process and many segments/process.
• It is a fixed or variable partition
• Hardware support has to include multiple base/limit pairs, with named segments by #, to index into table, hence virtual addresses become <segment #, offset>.

Paging

• It splits the virtual address space into multiple partition, each can go anywhere, external fragmentation is being solved by using fixed sized units in both physical and virtual memory.
• Need the OS to keep track.

Process Perspective of Paging

• Processes view memory as one contiguous address space from 0 through N that is, virtual address space (VAS) .
• Pages are scattered throughout the physical storage.
• A program cannot reference memory outside of its VAS, as the memory is invisible to it.
• Address "0x1000” maps to different physical addresses in different processes.

Paging: Translating Addresses

• It contains the virutal (virtual page number and offset).
• The virtual page number (VPN) is an index into a page table.
• The page table determines page frame number (PFN).
• Physical address is PFN::offset.
• It maps virtual page number (VPN) to page frame number (PFN) and has a one to one link between the page table entry (PTE) to the virtual address space.

Paging Example

• Pages are 4KB each.
• Offset is 12 bits (because 4KB = 212 bytes).
• VPN is 20 bits (32 bits is the length of every virtual address).
• Virtual address is 0x7468, then virtual page is 0x7 and offset is 0x468 as Page table entry 0x7 contains 0x2000 Page frame number is 0x2000.
• The seventh virtual page is at address 0x2000 (2nd physical page).
• The physical address = 0x2000 + 0x468 = 0x2468.

Page Table Entries (PTEs)

• Page table entries control mapping, contain modify, reference, valid and protection bits but also determine the page frame number (PFN) determines physical page.

Paging Advantages

• Memory is easily allocated due to being a fixed size chunk but that it is just extracted from the list.
• External fragmentation is gone.
• Enables to simplify protection and the chunks are the same size.

Paging Limitations

• Internal fragmentation may still exist, as the Proccess may not use memory in multiples of a page.
• Memory reference overhead, as it is more lookups per address lookup for page table then memory but also can grow significantly the required memory for the page table.