Pipelining vs Parallel Processing Quiz and Flashcards

Introduction to Pipelining and Its Performance

Pipelining is a technique of breaking down a sequential process into sub-operations, with each sub-operation executed in a dedicated segment that operates concurrently with all other segments.
Several computations can be in progress in distinct segments at the same time, thanks to the isolation provided by registers between each segment.
Pipeline organization is applicable for two areas of computer design: pipeline processing in data stream and instruction stream.
The structure of a pipeline organization can be represented simply by including an input register for each segment followed by a combinational circuit.
The organization of an instruction pipeline will be more efficient if the instruction cycle is divided into segments of equal duration, with a typical example being a four-segment instruction pipeline.
Arithmetic pipelines are mostly used in high-speed computers to implement floating-point operations, multiplication of fixed-point numbers, and similar computations encountered in scientific problems.
The execution sequence of instructions in a pipelined processor can be visualized using a space-time diagram.
RISC processor has a five-stage instruction pipeline to execute all the instructions in the RISC instruction set.
The performance of a pipelined processor is expressed in terms of speedup and throughput.
Hazards that arise in the pipeline prevent the next instruction from executing during its designated clock cycle, and there are three types of hazards: structural, data, and control hazards.
Structural hazards arise because there is not enough duplication of resources.
Data hazards arise due to two types of data dependence: true data dependencies and name dependences.Data Hazards and Introduction to Parallel Processors
There are three types of data hazards: true data dependence, output dependence, and anti-dependence.
True data dependence requires program order preservation and occurs when instruction j reads a register or memory location that instruction i writes.
Output dependence occurs when instruction i and instruction j write the same register or memory location, and requires ordering preservation.
Anti-dependence occurs when instruction j writes a register or memory location that instruction i reads, and renaming can be done to avoid it.
Control dependence determines the ordering of an instruction with respect to a branch instruction.
Control dependencies impose constraints on instruction execution with respect to a branch.
Dependences are properties of programs, and whether they cause pipeline hazards depends on the pipeline organization.
Data hazards can cause stalls in the pipeline and are classified as RAW, WAR, or WAW depending on the order of read and write accesses.
Conflict for resource use can cause a pipeline bubble, and pipelined datapaths require separate instruction/data memories or caches.
Control hazards occur when the destination of a branch is unknown, and instructions can't be fetched until it's resolved.
Parallel processing enables simultaneous data-processing to increase computational speed and throughput.
Parallel processing can be achieved by having multiple functional units that perform identical or different operations simultaneously.

Introduction to Pipelining and Its Performance

Pipelining is a technique of breaking down a sequential process into sub-operations, with each sub-operation executed in a dedicated segment that operates concurrently with all other segments.
Several computations can be in progress in distinct segments at the same time, thanks to the isolation provided by registers between each segment.
Pipeline organization is applicable for two areas of computer design: pipeline processing in data stream and instruction stream.
The structure of a pipeline organization can be represented simply by including an input register for each segment followed by a combinational circuit.
The organization of an instruction pipeline will be more efficient if the instruction cycle is divided into segments of equal duration, with a typical example being a four-segment instruction pipeline.
Arithmetic pipelines are mostly used in high-speed computers to implement floating-point operations, multiplication of fixed-point numbers, and similar computations encountered in scientific problems.
The execution sequence of instructions in a pipelined processor can be visualized using a space-time diagram.
RISC processor has a five-stage instruction pipeline to execute all the instructions in the RISC instruction set.
The performance of a pipelined processor is expressed in terms of speedup and throughput.
Hazards that arise in the pipeline prevent the next instruction from executing during its designated clock cycle, and there are three types of hazards: structural, data, and control hazards.
Structural hazards arise because there is not enough duplication of resources.
Data hazards arise due to two types of data dependence: true data dependencies and name dependences.Data Hazards and Introduction to Parallel Processors
There are three types of data hazards: true data dependence, output dependence, and anti-dependence.
True data dependence requires program order preservation and occurs when instruction j reads a register or memory location that instruction i writes.
Output dependence occurs when instruction i and instruction j write the same register or memory location, and requires ordering preservation.
Anti-dependence occurs when instruction j writes a register or memory location that instruction i reads, and renaming can be done to avoid it.
Control dependence determines the ordering of an instruction with respect to a branch instruction.
Control dependencies impose constraints on instruction execution with respect to a branch.
Dependences are properties of programs, and whether they cause pipeline hazards depends on the pipeline organization.
Data hazards can cause stalls in the pipeline and are classified as RAW, WAR, or WAW depending on the order of read and write accesses.
Conflict for resource use can cause a pipeline bubble, and pipelined datapaths require separate instruction/data memories or caches.
Control hazards occur when the destination of a branch is unknown, and instructions can't be fetched until it's resolved.
Parallel processing enables simultaneous data-processing to increase computational speed and throughput.
Parallel processing can be achieved by having multiple functional units that perform identical or different operations simultaneously.

Principles of Pipelining and Vector Processing

Vector processing involves large computations on multiple data things that a traditional computer with scalar processor cannot efficiently handle.
Vector processors use instruction pipeline and pipeline the data, functioning on multiple data at constant time.
Vector instructions can be classified as Vector-Vector Instructions, Vector-Scalar Instructions, Vector reduction Instructions, and Vector-Memory Instructions.
Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub-process being executed in a special dedicated segment that operates concurrently with the other segments.
Pipeline efficiency is determined by the accumulated rate of all stage utilizations, while pipeline throughput is the initiation rate or the average number of task initiations per clock cycle.
Interleaved Memory organization is a way of compensating for the relatively slow speed of DRAM by splitting memory into memory banks that can be accessed separately without any dependency on the other.
A systolic array is a network of processors that rhythmically compute and pass data through the system, and is an example of pipelining alongside parallel computing.
Systolic arrays have a large number of identical processors or process elements (PEs) that are organized in a well-union structure like a linear or 2-dimensional array.
Pipeline schedule optimization involves using non-compute delay stage into the original pipeline to provide the modified reservation table, resulting in a new collision vector and an enhanced state diagram.
Unifunctional pipeline performs a fixed function, while multifunctional pipeline can perform more than one function.
Static pipelines perform one function at a time, while dynamic pipelines allow several functions to be performed simultaneously.
Scalar and vector arithmetic pipelines differ mainly in the area of register files and control mechanism involved, with vector hardware pipelines often built as add-on options to a scalar processor or as an attached processor driven by a control processor.Overview of Pipeline Processor Design
Pipeline processors are designed to increase the speed of processing by breaking down instructions into smaller sub-processes.
Arithmetic pipeline processors have been designed with different stages, such as 8 stages in TI-ASC and 4 stages in Star-100.
Scalar base machine and superscalar machines use parameters to design pipeline processors, with instruction-level parallelism (ILP) being the maximum number of instructions that can be executed simultaneously.
A superscalar pipeline design utilizes multiple pipelines operating concurrently, with resource-shared multiple pipelines allowing for two instructions to be issued per cycle.
Linear pipelining decomposes a process into stages or segments with a processing circuit connected to the input latch of the next stage.
Non-linear pipeline processors, such as dynamic pipelines, allow for feed forward and feedback connections and are used to perform variable functions at different times.
Data hazards, branching, interrupts, and data dependency can cause pipeline processors to deviate from their normal performance.
The number of stages in a pipeline design, the clock pulse length, and the bottleneck stage are important factors to consider in pipeline design.
The execute stage in a superscalar pipeline design uses different functional units, such as adders, multipliers, load units, and logic units.
The look-ahead window in a superscalar pipeline design is used for instruction look-ahead to obtain better pipeline throughput.
A multifunction dynamic pipeline can evaluate different functions following different dataflow patterns.
In a pipeline processor, each stage transfers its intermediate result to the input latch of the next stage at every clock pulse.