SR Latch: Set-Reset Latch

Latches

• Basic storage elements in digital circuits that can hold a binary state indefinitely until directed by an input signal to switch states.
• Latches are level-sensitive storage elements.
• These operate with signal levels.
• Latches store binary information temporarily.
• They are used in asynchronous sequential circuits where an immediate response to input changes is required.
• Latches are building blocks for flip-flops, which are used in flip-flops.

SR Latch

• SR Latch is also known as Set-Reset Latch.
• Circuit with 2 cross-coupled NOR gates / NAND gates and 2 inputs labelled S for set and R for reset.
• Two useful states:
  • Q=1, Q'=0 implies set state
  • Q=0, Q'=1 implies reset state
• If both inputs are switched to 0 simultaneously, the device will enter an unpredictable/undefined/metastable state.
• With NOR version setting both inputs to 1 is forbidden.
• With NAND version setting both inputs to 0 is forbidden.
• Q & Q' is normal output and complementary output.

SR Latch with Control Input

• En (enable) is the control input.
• Quiescent condition: outputs of 2 additional NAND gates stay at the logic-1 level as long as the enable signal remains at 0.

Gate Level Implementation of SR Latch

• Example Verilog module:

module SR_latch (input S, R; output Q, Q_bar);
  nor (Q, R, Q_bar);
  nor (Q_bar, S, Q);
endmodule

Dataflow Implementation of SR Latch

• Example Verilog module:

module SR_latch (input S, R; output Q, Q_bar);
  assign Q = ~(R | Q_bar);
  assign Q_bar = ~(S | Q);
endmodule

Behavioral Implementation of SR Latch

• Example Verilog module:

module SR_latch (input S, R; output reg Q, Q_bar);
  always @ (*) begin
    case ({S, R})
      2'b00: ; // No change
      2'b01: begin Q = 0; Q_bar = 1; end // reset
      2'b10: begin Q = 1; Q_bar = 0; end // set
      2'b11: ; // invalid state
    endcase
  end
endmodule

D Latch

• Level-sensitive bistable circuit that stores a single bit of data.
• Eliminates invalid state of SR latch by ensuring that the D (data) input directly controls the output.
• This ensures a valid output.
• Used in registers and memory circuits for data storage.
• D Latches act as synchronizers between two different clock domains.
• Can be used in level-triggered sequential circuits.

D Latch Types

• Transparent: output follows D when the enable signal is HIGH.
• Gated: stores the value of D when the enable signal is LOW.

Gate Level Implementation of D Latch

• Example Verilog module:

module D_latch (input D, En; output Q, Q_bar);
  wire S, R;
  nand (S, D, En);
  nand (R, ~D, En);
  nor (Q, R, Q_bar);
  nor (Q_bar, S, Q);
endmodule

Dataflow Implementation of D Latch

• Example Verilog module:

module D_latch (input D, En; output Q, Q_bar);
  assign Q = En ? D : Q;
  assign Q_bar = ~Q;
endmodule

Behavioral Implementation of D Latch

• Example Verilog module:

module D_latch (input D, En; output reg Q);
  always @ (*) begin
    if (En)
      Q = D;
  end
endmodule

JK Latch

• An improvement over the SR Latch where the invalid case (S=1, R=1) is eliminated.
• When both J (set) & K (reset) are high, the output toggles (Q becomes Q').
• JK Latches are used in asynchronous sequential circuits.
• Avoids the invalid state of the SR latch (when both inputs are HIGH).
• Provides toggling functionality, useful in counters and memory elements.
• JK Latches work as building blocks for JK flip flops, used in synchronous circuits.
• Can be modified as a D/T latch by modifying inputs.

Gate Level Implementation of JK Latch

• Example Verilog module:

module JK_latch (input J, K, En; output Q, Q_bar);
  wire S, R;
  nand (S, J, En, Q_bar); // set input
  nand (R, K, En, Q);   // Reset input
  nand (Q, S, Q_bar);
  nand (Q_bar, R, Q);
endmodule

Behavioral Implementation of JK Latch

• Example Verilog module:

module JK_latch (input J, K, En; output reg Q);
  always @ (*) begin
    if (En) begin
      case ({J, K})
        2'b00: ;
        2'b01: {Q, Q_bar} = 2'b01; // Reset
        2'b10: {Q, Q_bar} = 2'b10; // Set
        2'b11: {Q, Q_bar} = {~Q, ~Q_bar}; // Toggle
      endcase
    end
  end
endmodule

T Latch

• A T Latch is a modification of the JK latch where both J & K inputs are tied together to form a single T input.
• This simplifies the design while maintaining the ability to store and toggle states.
• T Latches are useful in frequency dividers and counters.
• T Latches act as a basic building block for the T flip-flop used in synchronous circuits.
• Simplifies JK latch as J = K = T.

Gate Level Implementation of T Latch

• Example Verilog module:

module T_latch (input T, En; output Q, Q_bar);
  wire J, K;
  assign J = T;
  assign K = T;
  wire S, R;
  nand (S, J, En, Q_bar);
  nand (R, K, En, Q);
  nand (Q, S, Q_bar);
  nand (Q_bar, R, Q);
endmodule

Dataflow Implementation of T Latch

• Example Verilog module:

module T_latch (input T, En; output reg Q, Q_bar);
  always @ (*) begin
    if (En) begin
      if (T)
        {Q, Q_bar} = {~Q, ~Q_bar}; // Toggle
    end
  end
endmodule

Behavioral Implementation of T Latch

• Example Verilog module:

module T_latch (input T, En; output reg Q);
  always @ (*) begin
    if (En) begin
      if (T)
        Q = ~Q; // Toggle
    end
  end
endmodule

SR Flip Flop

• Clocked version of the SR latch.
• Its edge-triggered (either on rising/falling edge of a clock).
• A sequential circuit that changes only at clock edges.
• Eliminates glitches caused by level-sensitive latches.
• Used in synchronous circuits where precise control is required.
• Stores binary data in sequential logic circuits.
• Acts as a basic building block for more complex flip flops.

SR Flip Flop Types

• Using NAND (active HIGH input).
• Using NOR (active LOW input).
• Clocked SR (edge-triggered).

Gate Level Implementation of SR Flip Flop

• Example Verilog module:

module SR_ff (input S, R, CLK; output Q, Q_bar);
  wire Sn, Rn, Qa, Qb;
  nand (Sn, S, CLK);
  nand (Rn, R, CLK);
  nand (Qa, Sn, Qb);
  nand (Qb, Rn, Qa);
  assign Q = Qa;
  assign Q_bar = Qb;
endmodule

Dataflow Implementation of SR Flip Flop

• Example Verilog module:

module SR_ff (input S, R, CLK; output reg Q, Q_bar);
  always @ (*) begin
    case ({S, R})
      2'b00: ; // x change
      2'b01: begin Q = 0; Q_bar = 1; end // reset
      2'b10: begin Q = 1; Q_bar = 0; end // set
      2'b11: ; // invalid
    endcase
  end
endmodule

Behavioral Implementation of SR Flip Flop

• Example Verilog module:

module SR_ff (input S, R, CLK; output reg Q, Q_bar);
  always @ (posedge CLK) begin
    if ($sr)
      $display("Invalid state detected at time %0t", $time);
    else if (S)
      {Q, Q_bar} = 2'b10; // set
    else if (R)
      {Q, Q_bar} = 2'b01; // reset
    // No change handled implicitly
  end
endmodule

D Flip Flop

• Data / Delay flip-flop.
• It is a clocked version of D latch that ensures synchronized data storage.
• Unlike the latch, the D flip-flop is edge-triggered.

Need for D Flip Flop

• Eliminates timing hazards found in D latches.
• Used in synchronous circuits, ensuring precise control of data flow.
• Stores binary data with clock synchronization.
• Acts as a fundamental building block for registers, counters, and memory elements.

Gate Level Implementation of D Flip Flop

• Example Verilog module:

module D_ff (input D, CLK; output Q, Q_bar);
  wire nD, nclk, S, R;
  not (nD, D);
  not (nclk, CLK);
  nand (S, D, CLK);
  nand (R, nD, CLK);
  nand (Q, S, Q_bar);
  nand (Q_bar, R, Q);
endmodule

Dataflow Implementation of D Flip Flop

• Example Verilog module:

module d_ff (input D, CLK; output reg Q, Q_bar);
  always @ (posedge CLK) begin
    Q <= D;
    Q_bar <= ~D;
  end
endmodule

Behavioral Implementation of D Flip Flop

• Example Verilog module:

module d_ff (input D, CLK; output reg Q);
  always @ (posedge CLK) begin
    Q <= D;
  end
endmodule

JK Flip Flop

• Edge-triggered sequential circuit that overcomes limitations of SR flip flop.
• Ensures that T= K=1 results in a toggle (Q -> Q') instead of an invalid state.
• Eliminates the invalid state found in SR flip flop.
• Provides toggling functionality useful in counters.
• Widely used in registers and sequential circuits.
• Acts as a universal flip flop.

Gate Level Implementation of JK Flip Flop

• Example Verilog module:

module JK_ff (input J, K, CLK; output Q, Q_bar);
  wire S, R, Qa, Qb;
  nand (S, J, CLK, Q_bar);
  nand (R, K, CLK, Q);
  nand (Qa, S, Qb);
  nand (Qb, R, Qa);
  assign Q = Qa;
  assign Q_bar = Qb;
endmodule

Behavioral Implementation of JK Flip Flop

• Example Verilog module:

module JK_ff (input J, K, CLK; output reg Q);
  always @ (posedge CLK) begin
    if ( J && K)
      Q <= ~Q;
    else if (J)
      Q <= 1;
    else if (K)
      Q <= 0;
  end
endmodule

T Flip Flop

• A modification of the JK flip flop, and J and K inputs are tied together to form a single toggle (T) input.
• This ensures that whenever T=1, output toggles (Q -> Q').
• Otherwise, the output remains unchanged.
• T Flip Flops Need: frequency dividers and are useful in counters
• Acts as a fundamental building block for synchronous sequential circuits.
• It can be derived from the JK flip flop (J=K=T)

Gate Level Implementation of T Flip Flop

• Example Verilog module:

module T_ff (input T, CLK; output Q, Q_bar);
  wire J, K;
  assign J = T;
  assign K = T;
  wire S, R, Qa, Qb;
  nand (S, J, CLK, Q_bar);
  nand (R, K, CLK, Q);
  nand (Qa, S, Qb);
  nand (Qb, R, Qa);
  assign Q = Qa;
  assign Q_bar = Qb;
endmodule

Dataflow Implementation of T Flip Flop

• Example Verilog module:

module T_ff (input T, CLK; output reg Q, Q_bar);
  always @ (posedge CLK) begin
    if (T)
      {Q, Q_bar} <= {~Q, ~Q_bar};
  end
endmodule

Behavioral Implementation of T Flip Flop

• Example Verilog module:

module T_ff (input T, CLK; output reg Q);
  always @ (posedge CLK) begin
    if (T)
      Q <= ~Q;
  end
endmodule