SoftMC: Open-Source Infrastructure for DRAM Studies

SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies

• SoftMC is a DRAM infrastructure meant to analyze various aspects of existing DRAM chips like reliability and latency
• The aim is to develop reliable high-performance DRAM-based main memory in future systems
• SoftMC is an FPGA based platform
• It is used to control and test memory modules designed for the commonly used DDR Double Data Rate Interface
• SoftMC has two properties: it provides flexibility to thoroughly control memory behavior or implement a wide range of mechanisms using DDR Commands and it is easy to use as it provides a simple and intuitive high-level programming interface hiding low-level FPGA details
• Experimental results from SoftMC are consistent with prior studies on retention time in modern DRAM, validating the infrastructure
• It allows validation of recently-proposed mechanisms that rely on accessing recently-refreshed or recently-accessed DRAM cells faster than other DRAM cells
• SoftMC can test new ideas on existing memory modules, and characterize emerging non-volatile memory modules that obey the DDR standard

Introduction to DRAM and SoftMC

• DRAM (Dynamic Random Access Memory) is the predominant technology used to build main memory systems of modern computers
• Scaling DRAM leads to higher capacity main memories
• Challenges affecting reliability and performance occur as the process technology node scales to the sub-20 nm feature size range
• Cells store data as charge, leaking gradually over time, it requires periodic refreshes to maintain the correct data
• Smaller cells cause various reliability and performance issues
• Reliable operation of DRAM cells is a key challenge in future technology nodes
• Less charge in smaller cells impacts the DRAM cells reliability and performance
• Smaller cells make cells more susceptible to interference which can disrupt DRAM operation by flipping bits and potentially lead to system failure or security breaches
• Accessing a cell with less charge takes longer, increasing write latency
• DRAM latency is determined by the slowest cell in any chip and has not improved with technology scaling, being a critical system performance bottleneck
• New mechanisms are needed to improve reliability and performance of DRAM-based main memory systems which must be accurately characterized, analyzed, and understood in terms of reliability and latency
• Characterization and analysis is based on experimental studies of real DRAM chips, given the impact of a large number of factors including various types of cell-to-cell interference, inter- and intra-die process variation, random effects, operating conditions, internal organization and stored data patterns
• Experimental characterization and analysis is needed to improve the reliability and performance of future DRAM-based main memories at various levels
• Accessible testing infrastructure, that enables system users and designers to characterize real DRAM chips

Key Features

• The infrastructure tests any DRAM operation supported by the commonly-used DRAM interfaces to characterize cell behavior or evaluate impact of a mechanism on real DRAM chips
• Adopts different refresh rates for different cells
• It is easy to use

How it Works

• The infrastructure should be flexible to test cell behavior or evaluate a mechanism's impact
• It should be easy to use
• A need is identified for testing infrastructure with flexibility and easy to use properties for architects and designers
• It is possible for software and hardware developers to implement new tests or mechanisms without spending significant time and effort
• A testing infrastructure that requires circuit-level implementation, detailed knowledge of the physical implementation of DRAM data transfer protocols over the memory channel, or low-level FPGA-programming to modify the infrastructure would severely limit the usability of and limit the number of experts
• SoftMC is designed to be flexible and easy-to-use experimentally
• It implements all low-level DRAM operations available in a typical memory controller
• Users implement test routines and mechanisms in a high-level language that automatically gets translated into the low-level SoftMC operations in the FPGA
• SoftMC can be used to implement any DRAM test or mechanism consisting of DDR commands, without requiring significant effort
• Users can verify whether the test or mechanism works successfully on real DRAM chips by monitoring whether any errors are introduced into the data
• It offers a wide range of use cases that can implement any DRAM test to verify data integrity, such as characterizing the effects of variation within or across a DRAM chip

DRAM Operations

• When the memory controller receives a request to a row that is not already activated, it issues an ACTIVATE command with a row address to the DRAM
• The row decoder determines the wordline that corresponds to the requested row address and activates the cells
• Activated cells share charge with the bitlines, sense amplifiers detect data by observing the perturbation that charge sharing created on the bitlines, and fully restore the charge of the activated cells
• The sense amplifiers contain the data of the activated row
• READ or WRITE specifies a portion of data in the activated row and corresponds to the requested column address
• Some time after issuing the ACTIVATE command, the memory controller issues a column command which is READ or WRITE
• tRCD timing parameter restricts the minimum time interval between an ACTIVATE command and a column command guaranteeing transfers of data from the sense amplifiers to the memory channel
• The tWTR is obeyed during controller READ operation after any WRITE command is issued to an open row in any bank
• The tRTW is obeyed during controller WRITE operation after any READ command is issued to an open row in any bank
• During tWTR and tRTW, the DDR bus is switched between read and write modes, which is called bus turnaround
• Precharge, also known as access of a new row first requires preparing the DRAM bank
• Activating a new row whilst another row is currently activated requires precharge
• The activated row in the bank needs to be deactivated, by disconnecting and isolating the activated cells and prepares the sense amplifiers by charging bitlines
• tRAS specifies the minimum time interval between an ACTIVATE command and a PRECHARGE command to ensures activated cells are restored
• tWR (write recovery time) specifies the minimum time interval between the end of data transfer caused by a write command and a PRECHARGE command, to ensures that cells updated by the write operation are fully restored
• tRP specifies the minimum time between a PRECHARGE command and an ACTIVATE command, to ensures the precharge operation completes before the next activation
• A DRAM cell cannot retain its data permanently due to charge leakage which requires periodic refreshing
• The memory controller replenishes cell charge by refreshing each DRAM row periodically (typically every 64 ms)
• The refresh period is specified by a timing parameter tREFI
• Prior to issuing a REFRESH command to a rank/bank, the memory controller first precharges all activated rows in the DRAM rank or the activated row in the DRAM bank that the refresh operation

Contribution of the Paper

• Introduction of SoftMC, the first open-source FPGA-based experimental memory testing infrastructure
• Implements all low-level DRAM operations in a programmable memory controller exposed to the user and enables efficient characterization of modern DRAM chips and evaluation of mechanisms built on top of low-level DRAM operations
• The first publicly-available infrastructure that exposes a high-level programming interface to ease memory testing and characterization
• Provision of a prototype implementation of SoftMC with a high-level software interface for users and a low-level FPGA-based implementation of the memory controller released as a freely-available open-source tool
• Demonstration of the capability, flexibility, and programming ease of SoftMC by implementing two example use cases
• Demonstrated the effectiveness of SoftMC as a new tool to test existing or new mechanisms on existing memory chips and that the expected effect not observable in 24 modern DRAM chips from three major manufacturers