RISC & Controller Functions

RISC Instruction Set

• Uses frequently used simple instructions.
• Selects useful but uncomplicated instructions.
• Has fixed instruction length and fewer instruction formats/addressing modes.
• Only load/store instructions access memory.
• All other operations occur between registers.
• Employs pipelining.
• Has numerous general-purpose registers to reduce memory access.
• Primarily uses hardwired control logic, minimizing or eliminating microcode control.

Controller Functions & Components

• Functions: Fetches, analyzes, and executes instructions; manages components in an orderly fashion.
• Components:
  • Program Counter (PC): Stores instruction addresses.
  • Instruction Register (IR): Stores machine code of instructions.
  • Instruction Decoder (ID): Analyzes instruction format, addressing mode, and function.
  • Operation Control Signal Formation Unit: Generates control signals for component coordination.
  • Timing System: Provides timing signals.
  • Address Register: Stores the address of the memory location to be accessed.

Computer Operation

• On power-up, a reset signal is generated, setting the PC to the address of the first instruction.
• Instruction fetching occurs, and the PC increments.
• Decoding and control units generate control signals based on timing signals, which analyzes the instruction.
• Control signals direct components to perform operations (arithmetic, data access, address transfer), which executes the instruction.
• After instruction completion, the cycle restarts with instruction fetching based on the PC value.
• Computers operate by repeatedly fetching, analyzing, and executing instructions.

Von Neumann Architecture

• Features:
  • Uses binary to represent information.
  • Storage program and programs controlled by the controller for automated high-speed instruction.
  • Includes five components: arithmetic unit, controller, memory, input devices, and output devices.

SRAM & DRAM Comparison

• SRAM stores information using bistable flip-flop states, while DRAM stores information using the presence or absence of charge on a capacitor.
• DRAM requires refreshing to maintain information stability as charge leaks over time.
• Refresh methods include centralized, distributed, and asynchronous refreshing.

Hardwired vs. Microprogram Controllers

• Hardwired Controllers:
  • Signals are generated immediately by combinational logic based on the current instruction code, state, and timing.
  • Faster.
  • Complex, inflexible, and difficult to modify or expand.
  • Commonly used in RISC CPUs.
• Microprogram Controllers:
  • Control signals are stored in control memory (microprogram).
  • Slower.
  • More structured, easier to modify and expand.
  • Commonly used in CISC CPUs.
• Comparison:

CISC vs. RISC

• CISC (Complex Instruction Set Computer):
  • Instructions vary in format, have rich addressing modes, numerous/complex instructions, and often use microprograms.
• RISC (Reduced Instruction Set Computer):
  • Instructions are concise, fewer/simpler instructions, has many registers, uses hardwired control, and employs pipelining.
  • Only LOAD and STORE instructions access memory.

Interleaved Memory

• Organized with multiple memory modules, using low-order address bits for module selection.
• Consecutive physical units aren't in the same module, but rather dispersed across the memory modules.
• Adjacent module addresses are non-continuous.
• Suitable for pipelined parallel access.
• Achieves maximum bandwidth with full pipeline utilization or when accessing continuous units.

Memory Classification

• By Storage Medium: Semiconductor, magnetic, optical.
• By Access Method: Random access, sequential access, semi-sequential access.
• By Read/Write Capability: Read-write memory, read-only memory.
• By Volatility: Volatile (non-permanent), non-volatile (permanent).
• By System Role: Main memory, auxiliary memory, cache.

Computer Operation from Hardware Perspective

• Programs/data are input to memory via input devices.
• The controller fetches instructions to the IR, which are decoded.
• Micro-operation control signals are sent to the arithmetic unit, memory, or I/O devices to execute functions.

Interrupts

• Classified as internal or external based on the interrupt source.
• Process: At the end of each instruction cycle, an interrupt query signal is sent. If an interrupt exists, the interrupt hidden instruction is executed before interrupt handling. The return to the interruption then proceeds.
• Types: internal, external
• Interruption vector: entrance address of an interrupt service program
• Interrupt vector table: a table housing the types of termination and arrest vectors.

B/S vs. C/S

• B/S (Browser/Server): architecture used in browsers/servers; applicable to wide area networks.
  • Features unknown clients and slow speeds.
• C/S (Client/Server): architecture used in clients/servers; more secure and faster-paced.
  • Requires client installation.

CPU-Peripheral Exchange Methods

• Includes query method, interrupt method, DMA method, channel method, and I/O processor method.
• Query method: the CPU constantly inquires about input completion
• Interrupt method: inputs/outputs data via an interrupt service routine
• DMA method: an interface sends a DMA request, has total control to complete data transfer, with no CPU participation.
• Channel and DMA are similar

Southbridge & Northbridge

• Northbridge handles CPU and memory.
• Southbridge manages I/O.

Cache

• A high-speed buffer memory is closer to CPU that works faster.
• Mapping Methods:
  • Direct mapping (one-to-one).
  • Set-associative mapping (random within a set).
  • Fully associative mapping (fully random).

Locality Principles

• Temporal locality: A location accessed at one point is likely to be accessed again soon.
• Spatial locality: Locations near a recently accessed location are likely to be accessed soon (e.g., in arrays).

CPU Design Approaches

• First come first served, shorter process priority, time slice rotation, etc.

Parallel vs. Serial Communication

• Parallel: Transmits multiple bits simultaneously, uses more resources, faster within computers.
  • Computer internal bus architecture
• Serial: Transmits bits sequentially, slower, uses fewer resources, suitable for long distances.
  • Public telephone

Programming Languages

• Machine Language: Directly recognized and executed by computers.
  • Pros: Fastest execution, space-efficient, more comprehensive functions
  • Cons: Difficult to learn, understand, and use.
• Assembly Language: Uses symbolic language for human understanding.
  • Pros: Direct access to system interfaces, efficient compiled programs.
  • Cons: Difficult to learn, use, and prone to errors.
• High-Level Language: Uses simple writing similar to natural language.
  • Pros: Easy to learn/use, high versatility.
  • Cons: Numerous high-level language types exist today.

Single-Cycle vs. Multi-Cycle CPUs

• Single-Cycle: CPU completes instruction fetch, result acquisition, etc., in each cycle.
• Multi-Cycle: CPU execution divided into stages completed over multiple cycles to increase work efficiency and provide a basis for pipelining, and each cycle performs one of them.

Binary Encoding for Computers

• Physically easy to achieve.
• Simplifies storage and reduces errors.
• Arithmetic logic and simple operations

Microprogram Interpretation

• Upon power-up, the reset signal sends the address of the first instruction to the Program Counter (PC).
• An "instruction fetch" microinstruction is sent to the microinstruction register and ensures initialization of state bits or registers.
• When the voltage is stable, the computer automatically starts and generates beat potential and working pulses.
• The shutdown is not executed immediately until it finishes executing the current command to not corrupt restart of the computer.

Controller's Role in Arithmetic Unit Operation

• Arithmetic units can only perform calculation functions.
• The controller handles fetching instructions, analyzing them, fetching values, and submitting the data to the execution unit.

CPU & Memory Connections

• Connected via buses including data, address, and control buses.

Addressing Modes

• Direct addressing: Directly provides the memory address.
• Register addressing: Data is stored in a register.
• Register indirect addressing: Register contains the memory address.
• Indirect addressing: Provides an address that leads to the data's address.
• Base and indexed addressing: Adds an offset to a register's content.
• Register addressing is generally faster and more efficient at obtaining disc space.

Computer Hardware Metrics

• Machine word length.
• Clock speed (processing speed).
• Storage capacity.