memory

Memory Organization

Random Access Memory

A unit of digital information that most commonly consists of eight bits

A vector of bits that identifies a particular memory element (or collection of elements)

SRAM stores information in flip-flops, while DRAM stores information as electrical charges on capacitors

Nonvolatile

To store frequently executed instructions closer to the CPU

SDRAM synchronizes access with a clock, while DDR-SDRAM sends data twice per clock cycle

Recently referenced memory will be referenced again soon

The word is delivered to the processor from the cache

Little-endian and big-endian

RAM (Random Access Memory)

DRAM (Dynamic RAM)

Memory words close to recently referenced words will be referenced soon

PROM (Programmable Read-Only Memory)

2 bytes

8 bits

As an indexed array of words

$12$ memory words each of size $8$ bits

Address pins, data pins, and operation pins

$\text{Address pins} * \text{Data pins} = \text{Memory total size}$

26.5ns

512 Kbytes to 1 Mbytes

Uniform cache stores both instruction and data, while split cache internally divides into two caches for instructions and data.

0.87

7.33

1 Gbyte to 4 Gbytes

The fraction of all memory accesses found in the cache

$10.25ns$

Inside the CPU chip itself

To make processor appear as a single memory unit but much faster than it really is

Measured in nanoseconds for DRAM and in picoseconds for SRAM

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Random Access Memory (RAM) is a type of memory organized such that data can be transferred to or from any cell (or collection of cells) in a time that is not dependent upon the particular cell selected. Its organization refers to the basic architectural structure of a memory in terms of how data is accessed.

A memory address is a vector of bits that identifies a particular memory element (or collection of elements). It is significant in computer memory systems as it helps in locating and accessing specific memory elements for data transfer.

The typical data sizes are: a single binary digit for a bit, and a unit of digital information that most commonly consists of eight bits for a byte.

A byte (of 8 bits) has a limited range of 256 values. When a value is beyond this range, it has to be stored in multiple bytes to accommodate the larger range of values.

Average access time = 10 + (1-0.9) * 100 = 10 + 0.1 * 100 = 20 ns

Performance Improvement = Time without cache / Time with cache = 1150 / 150 = 7.66

Mean access time = 5 + (1 - 0.95) * 100 = 5 + 0.05 * 100 = 9.75 ns

Uniform cache stores both instruction and data, and does not allow fetching instruction and data to happen at the same time. Split cache is internally divided into two caches: one stores only instructions (I-cache) and the other stores only data (D-cache), allowing parallel processing of instructions and used with the pipelined processor.

Hit ratio is the fraction of all memory accesses that are found in the cache, calculated as $h = \frac{\text{number of hits}}{\text{total memory accesses}}$. Miss ratio is calculated as $1-h$.

Level 1 cache (L1 Cache) is located inside the CPU chip, usually split cache with a typical size of 16 Kbytes to 64 Kbytes. Level 2 cache (L2 Cache) is connected to the CPU by a very high-speed bus, slower than L1 cache but much larger in size, usually uniform with a typical size of 512 Kbytes to 1 Mbytes. Level 3 cache (L3 Cache) is originally located on the motherboard, faster than the main RAM memory, usually uniform with a typical size of a few megabytes.

Word mean access time = c + (1 - h) * m

Temporal locality refers to the tendency of a computer system to access the same memory locations repeatedly within a short period of time. Spatial locality refers to the tendency of a computer system to access data at addresses near the ones it has recently accessed.

The purpose of using multilevel caches in a processor is to provide faster access to frequently used data and instructions, reducing the average access time and improving overall system performance.

The improvement in performance is calculated using the equation $\text{Performance Improvement} = \frac{\text{Time without cache}}{\text{Time with cache}}$.

The main improvement achieved by using split cache over uniform cache is the ability to allow parallel processing of instructions and data fetching, which is essential for pipelined processors.

Dynamic RAM (DRAM) chips for personal computers have access times of 50 to 150 nanoseconds, where 1 ns = $10^{-9}$ second. Static RAM (SRAM) has access times as low as 10 nanoseconds.

The two types of RAM are Static RAM (SRAM) and Dynamic RAM (DRAM). SRAM stores information in flip-flops, while DRAM stores information as electrical charges on capacitors.

SDRAM synchronizes access with a clock, while DDR-SDRAM sends data twice per clock cycle.

Little-endian stores bytes representing numbers starting from the rightmost byte, while big-endian starts from the leftmost byte.

Cache memory is a small, fast memory that stores frequently executed instructions closer to the CPU, based on the principle of locality of reference.

The two types of locality of reference are temporal locality and spatial locality. Temporal locality means recently referenced memory will be referenced again soon, while spatial locality means memory words close to recently referenced words will be referenced soon.

The two types of ROM are PROM, EPROM, EEPROM, and Flash Memory. ROM contains unchangeable data and is nonvolatile, used in various applications including storing the operating system program.

Cache read operation involves checking if the word is in the cache, with a hit resulting in delivery to the processor, and a miss leading to loading from main memory.

The two cache write policies are Write Through and Write Back policies. Each has its advantages and disadvantages.

ROM contains unchangeable data and is nonvolatile, used in various applications including storing the operating system program.

Little-endian stores bytes representing numbers starting from the rightmost byte, while big-endian starts from the leftmost byte.

Little-endian and big-endian are two systems for storing bytes representing numbers in memory words, used in different processors.

RAM allows direct access to memory words by specifying their addresses with the same access time regardless of location. It is organized such that data can be transferred to or from any cell in a time that is dependent upon the particular cell selected.

At least two bytes

Word size is processor dependent and is normally in multiples of 8, such as 8, 16, 32, or 64 bits.

Memory is built from millions of storage cells organized as an indexed array of words, with each word assigned a location number called the word address.

Address pins, data pins, and control pins for memory operations.

Memory size can be interpreted as the total memory size being 96 bits, which can be 96 memory words each of size one bit, or 12 memory words each of size 8 bits, and so on.

Memory operations require data, address, and operation control, typically involving read and write operations.

The memory total size is 20480 bits, with MDR size of 10 bits and MAR size of 11 bits.

The memory is connected to the processor by address, data, and control lines, with the address lines connected to the MAR and the data lines connected to the MDR.

For a memory chip of size 512K x 8, there are 512 KB = 2^9 * 2^10 = 2^19 bits, with 3 control pins, and the size of MDR is 8 and the size of MAR is 19.

Random Access Memory (RAM) is organized such that data can be transferred to or from any cell in a time that is dependent upon the particular cell selected.

For a memory with 3 address bits and 8 data bits, there are 8 words and each word is of size 8 bits.

For a memory chip of size 512K x 8, there are 512 KB = 2^9 * 2^10 = 2^19 bits, with 3 control pins, and the size of MDR is 8 and the size of MAR is 19.

bits

eight

bytes

cell

six

rightmost, leftmost

main

capacitors

CPU

power

Flash

Write Back

processors

DDR

nonvolatile

soon

eight bits

19

11

MDR

processor

27ns

two

12

8

address pins, data pins, and control pins

bytes

read

Temporal locality refers to the tendency of a computer system to access the same set of data or instructions multiple times within a short time period, while spatial locality refers to the tendency of a computer system to access data at addresses near the ones it has recently accessed. An example of temporal locality is a loop that iterates over an array, while an example of spatial locality is accessing elements of an array that are stored close to each other.

Uniform cache stores both instruction and data, while Split cache is internally divided into two caches, one for instructions (I-cache) and the other for data (D-cache).

The hit ratio is the fraction of all memory accesses that are found in the cache and is calculated as follows: If the number of times the CPU accesses the same memory location to Read or Write within a very short period of time is K, then the hit ratio h is given by: $h = \frac{K-1}{K}$. The miss ratio is calculated as $1-h$.

The five levels of memory hierarchy include Registers, L1 Cache, L2 Cache, Main Memory (RAM), and Secondary Storage (Hard Disk). Registers are the fastest but smallest in size, followed by L1 Cache, L2 Cache, Main Memory, and Secondary Storage. Each level is larger but slower than the previous one, with the goal of providing fast access to the most frequently used data and instructions.

The improvement in performance that results from using the cache can be obtained by: $Performance Improvement = \frac{Time without cache}{Time with cache}$

The purpose of cache memory is to provide fast access to frequently used instructions and data, thereby reducing the average time it takes to access memory and improving overall system performance.

The purpose of cache memory is to reduce the average time it takes to access memory by storing frequently used instructions and data closer to the CPU. It is based on the principle of exploiting the principle of locality, which states that programs tend to access a relatively small portion of their address space at any given time.

Cache read operation involves checking if the word is in the cache. If the word is found in the cache, it results in a cache hit, and the word is delivered to the processor. If the word is not found in the cache, it results in a cache miss, and the word needs to be fetched from the main memory.

The two types of ROM are PROM (Programmable Read-Only Memory) and EPROM (Erasable Programmable Read-Only Memory). PROM is programmed during manufacturing and cannot be modified, while EPROM can be erased and reprogrammed using ultraviolet (UV) light.

The purpose of Read Only Memory (ROM) is to store firmware and essential system instructions that do not change over time. It is considered nonvolatile because its contents are retained even when the power is turned off.

The main purpose of using multilevel caches in a processor is to provide a hierarchy of fast, small-sized caches closer to the CPU, which can store frequently accessed data and instructions. This helps in reducing the average memory access time and improving the overall performance of the processor.

The interpretation of total memory size being 96 bits means that each memory location or word in the system is represented using 96 bits, which includes the addressable bits and the data bits. This indicates the total capacity and addressability of the memory system.

Memory = A collection of storage cells together with the necessary circuits to transfer information to and from them. Memory Organization = The basic architectural structure of a memory in terms of how data is accessed. Random Access Memory (RAM) = A memory organized such that data can be transferred to or from any cell (or collection of cells) in a time that is not dependent upon the particular cell selected. Memory Address = A vector of bits that identifies a particular memory element (or collection of elements).

Bit = A single binary digit. Byte = A unit of digital information that most commonly consists of eight bits. Byte (of 8 bits) = A unit of digital information that has a limited range of 256 values. Multiple Bytes = Used to store values beyond the range of a single byte.

RAM = Stores programs & data, with a memory organization allowing transfer to or from any cell in constant time. ROM = Non-volatile memory used to store firmware for booting up the computer system. Cache = High-speed memory used to temporarily store frequently accessed data for quicker access by the CPU. Flash Memory = Non-volatile memory commonly used in storage devices such as USB drives and SSDs.

Spatial Locality = The phenomenon where accessing a particular memory location makes it likely that nearby memory locations will also be accessed soon. Temporal Locality = The phenomenon where recently accessed memory locations are likely to be accessed again soon. Memory Data Read Operation = Involves transferring data from a specified memory location to the CPU for processing. Memory Data Write Operation = Involves transferring data from the CPU to a specified memory location for storage.

Static RAM (SRAM) = Stores information in flip-flops Dynamic RAM (DRAM) = Stores information as electrical charges on capacitors Synchronous DRAM (SDRAM) = Synchronizes access with a clock DDR-SDRAM = Sends data twice per clock cycle

Volatile memory = Loses its content when power is turned off Read Only Memory (ROM) = Contains unchangeable data and is nonvolatile Cache memory = Small, fast memory that stores frequently executed instructions closer to the CPU Little-endian = Stores bytes representing numbers starting from the rightmost byte

Temporal locality = Means recently referenced memory will be referenced again soon Spatial locality = Means memory words close to recently referenced words will be referenced soon Cache read operation with a hit = Results in delivery to the processor Cache read operation with a miss = Leads to loading from main memory

PROM = Programmable Read Only Memory, once programmed, cannot be changed EPROM = Erasable Programmable Read Only Memory, can be erased and reprogrammed multiple times EEPROM = Electrically Erasable Programmable Read Only Memory, can be erased and reprogrammed electrically Flash Memory = Can be electrically erased and reprogrammed in blocks; used in USB drives, memory cards, etc.

Uniform Cache = Will not allow fetching instruction and data to happen at the same time. Split Cache = Allows parallel processing of instructions and used with the pipelined processor.

Level 1 cache (L1 Cache) = Located inside the CPU chip itself. Level 2 cache (L2 Cache) = Typical size is 512 Kbytes to 1 Mbytes. Level 3 cache (L3 Cache) = Typical size is few megabytes.

Dynamic RAM (DRAM) = Typically used for personal computers. Static RAM (SRAM) = Has faster access times compared to DRAM.

Hit ratio = Fraction of all memory accesses found in the cache. Miss ratio = Fraction of memory accesses not found in the cache. Mean access time = Time a program or device takes to locate a single piece of information and make it available to the computer for processing. Performance Improvement = Calculated using the equation $Performance Improvement = \frac{Time without cache}{Time with cache}$.

Main memory = Typical size is few megabytes. Cache Memory = Typical size is 16 Kbytes to 64 Kbytes.

Temporal locality = Refers to accessing the same memory location multiple times within a short period of time. Spatial locality = Refers to accessing nearby memory locations around a recently accessed location.

Address pins = Used to specify the location of data in memory Data pins = Responsible for transferring data between memory and processor Control pins = Manage memory operations such as read and write Word address = Location number assigned to each word in memory

96 bits = Could be 96 memory words each of size one bit, or 12 memory words each of size 8 bits, and so on 512K x 8 = Equivalent to 29 * 210 = 219 bits, with 512 KB of total size 2K x 10 = Results in 20480 bits of total size 3 address bits and 8 data bits = Leads to a memory with 8 words, each of size 8 bits

Indexed array of words = Millions of storage cells organized as an array, with each word having a word address Random Access Memory (RAM) = Connected to the processor by address, data, and control lines Read Only Memory (ROM) = Contains unchangeable data and is nonvolatile Cache memory = Improves performance by storing frequently accessed data

512K x 8 = Has a size of 512 KB = (2^9 \times 2^{10} = 2^{19}) bits, with a size of MDR as 8 bits and MAR as 19 bits 2K x 10 = Involves 11 address pins, 10 data pins, and results in a memory total size of 20480 bits, with MDR size of 10 bits and MAR size of 11 bits 3 address bits and 8 data bits = Yields a memory with 8 words, each of size 8 bits Processor-dependent word size = Typically in multiples of 8 such as 8, 16, 32, or 64 bits