Operating System Basics

Operating System Overview

• Uses hardware resources from one or more processors
• Aims to provide services to system users
• Manages secondary memory and I/O devices

Basic Computer Elements

• Processor, main memory, I/O modules, and a system bus are fundamental elements
• System bus facilitates communication among processors, main memory, and I/O modules

Processor Details

• Features two internal registers: Memory Address Register (MAR) and Memory Buffer Register (MBR)
• MAR specifies the address for the next read or write operation
• MBR contains data written into memory or receives data read from memory
• I/O address register and I/O buffer register are also important components

Main Memory Characteristics

• Volatile, often referred to as real or primary memory

I/O Modules Include

• Secondary memory devices, communications equipment, and terminals

Processor Registers: User-Visible

• User-visible registers enable programmers to minimize main memory references by optimizing register use
• Programmers can access these registers using assembly codes

Processor Registers: Control and Status

• Control registers control various aspects, including memory management and the CPU's operation modes
• Status registers hold flags indicating the outcome of operations or the state of the processor, such as FLAGS or EFLAGS register

User-Visible Registers Details

• Accessible to all programs (application and system programs)
• Can be referenced by machine language
• Types include data, address, index register (adds an index to a base value for the effective address), segment pointer (memory referenced by segment and offset), and stack pointer (points to top of stack)

Control and Status Registers

• Program Counter (PC) contains the address of the next instruction to be fetched
• Instruction Register (IR) contains the most recently fetched instruction
• Program Status Word (PSW) contains status information
• Condition codes or flags are bits set by processor hardware as a result of operations, indicating positive, negative, zero, or overflow results

Instruction Execution: Two-Step Process

• A processor reads (fetches) instructions from memory
• The processor executes each instruction

Instruction Fetch and Execute

• The processor retrieves instructions from memory
• PC holds address of the instruction to be fetched next and is incremented after each fetch

Instruction Register

• Fetched instruction is loaded into the instruction register
• Types of instructions include processor-memory, processor-I/O, data processing, and control

Interrupts

• Interrupt normal processor sequencing because most I/O devices are slower than the processor
• Classes include Program, Timer, I/O and Hardware failure

Interrupt Stage Actions

• Processor checks for interrupts; if present, suspends the current program's execution
• Executes an interrupt-handler routine

Multiprogramming Environment

• Processor executes more than one program
• Program execution sequence depends on relative priority and I/O wait times
• After an interrupt handler completes, control may shift due to various factors

Control Shifts After Interrupt Handling Due To

• Context switch, higher priority process, error or exception handling, nested interrupts, or system Calls

Memory Hierarchy Characteristics

• Faster access has greater cost per bit verses greater capacity having a smaller cost per bit
• Memory hierarchy includes Registers, Cache, Main memory, Outboard storage, and Offline storage

Hierarchy Trends

• It goes down the hierarchy (from faster to slower memory), cost per bit decreases, capacity increases, access time increases, and the frequency of access to the memory by the processor decreases

Secondary Memory Traits

• It is auxiliary, external, nonvolatile, and is used to store program and data files

Cache Memory Benefits

• Processor speed is faster than memory access speed
• Exploits the principle of locality with a small fast memory – programs access nearby memory locations and recently used data frequently

Cache Principles Explained

• Cache: Contains a portion of main memory
• The processor checks the cache first and, if not found, the relevant memory block is read into the cache
• Due to locality of reference, future memory references are likely within that block
• Mapping function determines which cache location the block will occupy

Replacement Algorithm

• Chooses a block to replace using - Least Recently Used (LRU), First in First Out (FIFO), or Least Frequently Used (LFU)

Cache Write Policy

• It dictates when the memory write operation takes place
• Can occur every time the block updates, when the block is replaced to minimize write operations, and can leave main memory which are in an obsolete state

Programmed I/O Characteristics

• I/O module performs the action (not processor)
• Sets appropriate bits in the I/O status register
• No interrupts occur; processor checks status until operation is complete

Interrupt-Driven I/O Process

• The processor is interrupted when the I/O module is ready to exchange data
• The processor saves the program's context and starts executing the interrupt-handler
• No needless waiting, but it consumes processor time since every read or written word passes through the processor

Direct Memory Access (DMA)

• It transfers data blocks directly to or from memory
• An interrupt is sent upon completion, which is more efficient