Podcast
Questions and Answers
The memory has as many ______ as there are time slots.
The memory has as many ______ as there are time slots.
cells
The time switch works well for a single ______–outlet switch.
The time switch works well for a single ______–outlet switch.
inlet
The data store is ______ with capacity to store one full frame of data.
The data store is ______ with capacity to store one full frame of data.
RAM
The speech data store is ______ bytes long for DS1 (1.544 Mbps) with 24 channels of 8 bits.
The speech data store is ______ bytes long for DS1 (1.544 Mbps) with 24 channels of 8 bits.
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Control is associated with ______ lines and specify which inputs are to be connected to the associated outputs.
Control is associated with ______ lines and specify which inputs are to be connected to the associated outputs.
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T = 1/(2*______ Rate)
T = 1/(2*______ Rate)
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A time slot represents one ______ channel.
A time slot represents one ______ channel.
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The time-slot counter or processor is a functional block of the ______.
The time-slot counter or processor is a functional block of the ______.
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The time duration of an 8-bit time slot in the DS1 case is ______ µsec.
The time duration of an 8-bit time slot in the DS1 case is ______ µsec.
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The writing of incoming time slots into the speech memory can be controlled by a ______ counter.
The writing of incoming time slots into the speech memory can be controlled by a ______ counter.
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The MUS/TSI/DEMUX has two basic memory blocks: 1) Memory for ______, and 2) Memory for control.
The MUS/TSI/DEMUX has two basic memory blocks: 1) Memory for ______, and 2) Memory for control.
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If the memory cycle time is 125 nano seconds, then maximum number of slots will be ______, which can accommodate 250 connections.
If the memory cycle time is 125 nano seconds, then maximum number of slots will be ______, which can accommodate 250 connections.
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The implementation complexity for an STS switch with 2048 channels organized in ______ TDM lines, with 8 bits/channel, 128 channels/frame is given by.
The implementation complexity for an STS switch with 2048 channels organized in ______ TDM lines, with 8 bits/channel, 128 channels/frame is given by.
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The probability of having a link busy is ______ and the maximum blocking probability for the STS switch is 0.002.
The probability of having a link busy is ______ and the maximum blocking probability for the STS switch is 0.002.
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The maximum blocking probability for the STS switch is ______.
The maximum blocking probability for the STS switch is ______.
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The number of channels per frame is ______.
The number of channels per frame is ______.
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The total number of channels is ______.
The total number of channels is ______.
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The number of bits per channel is ______.
The number of bits per channel is ______.
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The probability that the same time slot on a different ______ is chosen by the other subscribers on the same inlet.
The probability that the same time slot on a different ______ is chosen by the other subscribers on the same inlet.
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The Implementation Complexity IC is equal to Nx + ______100.
The Implementation Complexity IC is equal to Nx + ______100.
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The number of crosspoints will be significantly decreased, whilst the number of ______ will be increased.
The number of crosspoints will be significantly decreased, whilst the number of ______ will be increased.
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The TS structure is of ______ nature.
The TS structure is of ______ nature.
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A and B can be moved to the same time slot but during that time slot, the ______ line can be connected to C's line or D's line but not both.
A and B can be moved to the same time slot but during that time slot, the ______ line can be connected to C's line or D's line but not both.
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The Highest contribution of S-stage could be reduced by ______ the TDM lines.
The Highest contribution of S-stage could be reduced by ______ the TDM lines.
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STS is more efficient when ______ is greater than 0.2
STS is more efficient when ______ is greater than 0.2
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The number of crosspoints for S stage is given by ______ squared
The number of crosspoints for S stage is given by ______ squared
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The total number of memory bits for S and T stages is given by ______ log2 N plus ______ bits
The total number of memory bits for S and T stages is given by ______ log2 N plus ______ bits
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The number of channels in each link is ______ for the given 131,072-channel TSSST switch
The number of channels in each link is ______ for the given 131,072-channel TSSST switch
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The maximum blocking probability of the TSSST switch is ______
The maximum blocking probability of the TSSST switch is ______
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The number of TDM input links is ______ for the given 131,072-channel TSSST switch
The number of TDM input links is ______ for the given 131,072-channel TSSST switch
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Study Notes
Time-Slot Interchange (TSI) and Time Switch (T)
- A time switch handles 23 stations besides the calling subscriber, with 24 cells.
- Time-slot interchange: time switch (T) uses sequential write and random read, or random write and sequential read.
- Data store is RAM with capacity to store one full frame of data; for DS1, it is 24 bytes long.
- Two ways to handle a time switch:
- Sequential Write/Random Read: time-slots are written into the speech memory as they appear in the incoming bit stream.
- Random Write/Sequential Read: incoming time-slots are written into memory in the order of appearance in the outgoing bit stream (desired output order).
Switch Matrix Control (I)
- Cross-point selection within a matrix can be done in two ways:
- Output associated control: control is associated with output lines and specify which inputs are to be connected to the associated outputs.
- Input Associated control: control is associated with input lines and specify to which outputs the respective inputs are to be connected.
Time-Switch or TSI
- Has three basic functional blocks:
- Memory for speech
- Memory for control
- Time-slot counter or processor
- Data store memory is accessed twice during each link time slot.
- The required memory operation speed t is: t = 1/(2*Slot Rate)
Drill Problem
- If the memory cycle time is 125 nano seconds, then the maximum number of slots will be 500, which can accommodate 250 connections.
- Implementation complexity for an STS switch with 2048 channels organized in 16 TDM lines, with 8 bits/channel, 128 channels/frame.
Three Stage Switch Combinations
- The TS structure is of blocking nature.
- A and B are the subscribers using different time slots on the same line want to connect to two subscribers C and D using the same time slot on different lines.
- Implementation complexity: p STS is more efficient; p > 0.2: IC for STS > IC for TST => TST is more efficient.
- Having this result, in practice TST is preferred; eventually, for large switches, TST could be replaced by TSSST.
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Description
Learn about the two approaches to handling time switches in MUS/TSI/DEMUX systems: Sequential Write/Random Read and Random Write/Sequential Read. Understand the difference between these methods and how they affect the output order. Test your knowledge of time-slot handling in speech memory!
