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Questions and Answers
How can drain-induced barrier lowering (DIBL) effect be modeled?
As a coefficient, typically on the order of 0.1
What does DIBL cause to happen to Ids in saturation as Vds increases?
Increase
What is the drain-induced barrier lowering (DIBL) effect most pronounced in?
Short-channel transistors
What is the impact of DIBL on subthreshold leakage at high Vds?
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In the long-channel transistor I-V model, when does current flow from source to drain?
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How does current behave below threshold in real transistors?
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What happens to the current when the gate voltage falls below Vt?
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What is the value of the DIBL coefficient typically on the order of?
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In the inverter, what is the state when Vgs is high?
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What does DIBL effect cause to happen to subthreshold leakage at high Vds?
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