MIPS Instruction Formats

Machine Language/Machine Instruction

• Computers operate using 1s and 0s
• Machine language involves the binary representation of instructions
• MIPS instructions use a 32-bit format, which ensures simplicity and regularity for both data and instructions

Instruction Formats

• R-Type: Uses register operands and 2 source registers
• I-Type: Uses an immediate operand, which includes a constant readily available
• J-Type: Designed for jumping operations

R-Type Instructions

• Involves register-type operations
• Uses 3 register operands
  • Rs and Rt are source registers
  • Rd is the destination register
• op specifies the operation code or opcode
  • For R-type instructions, the opcode is 0
• funct specifies the function of the instruction
  • Opcode and function combined tell the computer what operation to perform
• shamt specifies the shift amount specifically for shift instructions
  • Otherwise its value is 0
• Instruction format is as follows: op (6 bits), rs (5 bits), rt (5 bits), rd (5 bits), shamt (5 bits), funct (6 bits)
• In assembly code, the destination register comes first, but in machine code instruction it comes last

R-Type Example

• For "add $s0, $s1, $s2" in assembly:
  • op is 0, rs is 17, rt is 18, rd is 16, shamt is 0, and funct is 32
• O in opcode indicates "R type" and 32 in the function field indicates addition

I-Type Instructions

• Designed for immediate-type operations
• Uses 3 operands
  • Rs and Rt are register operands
  • Imm is a 16-bit two's complement immediate value
• op field contains the opcode
  • Operation is completely determined by the opcode
• Instruction format is as follows: op (6 bits), rs (5 bits), rt (5 bits), imm (16 bits)
• The rt register is listed first in assembly code, but comes last in the register field in machine code
• The immediate is used in the processor which involves: instruction memory + ALU + data memory + register

I-Type Example

• In addi $t0, $s3, -12:
  • op is 8, rs is 19, rt is 8, and imm is -12
• Branch instructions such as beq, do not include destination registers

J-Type Instructions

• Used for jump-type instructions
• 26-bit address operand (addr)
• Instruction format is: op (6 bits), addr (26 bits)

Instruction Format Review

• The op field is present in all instruction types (R, I, and J)
• R-Type includes op, rs, rt, rd, shamt, and funct
• I-Type includes: op, rs, rt, and imm
• J-Type includes: op, and addr

Bit Numbers of Different Fields in Instructions

• The following bit numbers will be used in single-cycle processor design
• Opcode uses bits 31-26
• Rs uses bits 25-21
• Rt uses bits 20-16
• Rd (R type only) uses bits 15-11
• Funct (R type) uses bits 5-0
• Immediate (I type) uses bits 15-0
• Address (J type) uses bits 25-0

Interpreting Machine Language Code

• Begin with the opcode
• Opcode indicates how to parse the remaining bits
• When the opcode is all zeros, then:
  • R-Type instruction
  • Function bits further specify the instruction
• Otherwise, the opcode specifies the required instruction

The Power of the Stored Program

• Both 32-bit instructions and data are stored in memory
• Applications (like text editors or video games) only differ by sequence of instructions
• Executing a new program requires:
• No rewiring
• Simply storing the new program in memory
• Processor hardware executes the program using:
• Instructions fetched/read from memory in sequence
• Performing the specified operation
• The program counter (PC) tracks the current instruction
• In MIPS program execution starts at a memory address of 0x00400000

Common High-Level Software Constructs

• High-level languages include: C, Java, Python
  • They are written at a higher level of abstraction
• Include: if/else statements, for loops, while loops, arrays, function calls

Arithmetic/Logical Instructions

• and, or, xor, nor
  • and is useful for masking bits by isolating specific portions of data
  • or is useful for combining bit fields from multiple sources into one value
  • nor is useful for inverting bits
• andi, ori, xori
  • Use 16-bit immediate values that are zero-extended
  • nori is not needed

Shift Instructions

• sll is for shift left logical:
  • Shifts bits to the left, padding with zeros
• srl is for shift right logical:
  • Shifts bits to the right, padding with zeros
• sra is for shift right arithmetic:
  • Shifts bits to the right, filling with sign bit (to maintain proper sign for signed numbers)

Generating Constants

• Uses addi for 16-bit constants
• Uses load upper immediate (lui) and ori for 32-bit constants