Microprocessor Concepts Quiz

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Questions and Answers

What is the effect of the instruction 'MOV AX, 5000H'?

  • It moves the value of AX into 5000H.
  • It clears the AX register.
  • It moves the value of AX into a memory location at 5000H.
  • It moves the value 5000H into the AX register. (correct)

How many bytes are pushed onto the stack by the instruction 'PUSH AX'?

  • 1 byte
  • 2 bytes (correct)
  • 4 bytes
  • 8 bytes

Which segment does the base pointer (BP) reference when addressing memory?

  • Stack segment (SS) (correct)
  • Code segment (CS)
  • Data segment (DS)
  • Extra segment (EX)

What does the instruction 'JMP [BX]' do?

<p>It jumps to the address stored at the memory location pointed by BX. (A)</p> Signup and view all the answers

Which of the following statements about the stack is true?

<p>The stack follows a LIFO structure. (B)</p> Signup and view all the answers

When data is popped from the stack, which bits are removed from the location addressed by SP?

<p>Only the low-order 8 bits. (D)</p> Signup and view all the answers

Which register consists of 32 bits in 80386 and above?

<p>CX (B)</p> Signup and view all the answers

How many bytes are popped from the stack by the instruction 'POP EBX'?

<p>4 bytes (A)</p> Signup and view all the answers

What is the outcome of multiplying two 8-bit numbers?

<p>16-bit product (B)</p> Signup and view all the answers

Which instruction is used to subtract the contents at memory location addressed by DI from AX?

<p>SUB AX, [DI] (A)</p> Signup and view all the answers

What does the IMUL instruction signify?

<p>Multiplication (C)</p> Signup and view all the answers

What does the instruction MUL CL perform?

<p>AL is multiplied by CL, the signed product in AX. (B)</p> Signup and view all the answers

What is the result when two 16-bit numbers are multiplied?

<p>32-bit product (B)</p> Signup and view all the answers

When two 16-bit numbers are multiplied, where does the resulting product appear?

<p>DX-AX (D)</p> Signup and view all the answers

Which instruction is used to multiply AL with the byte contents at the memory location addressed by BX?

<p>MUL BYTE PTR [BX] (D)</p> Signup and view all the answers

What does the IDIV CL instruction accomplish?

<p>AX is divided by CL, signed quotient in AL and signed remainder in AH. (A)</p> Signup and view all the answers

What is the meaning of the DIV SI instruction?

<p>DX-AX is divided by SI, unsigned quotient in AX and unsigned remainder in DX. (B)</p> Signup and view all the answers

Which arithmetic instruction divides AX by the byte at the BP memory location with the signed quotient in AL and signed remainder in AH?

<p>IDIV BYTE PTR [BP] (D)</p> Signup and view all the answers

Which instruction divides DX-AX by the word contents at the BP memory location with the unsigned quotient in AX?

<p>DIV WORD PTR [BP] (C)</p> Signup and view all the answers

Which of the following statements is true regarding the effect on the flag register?

<p>Arithmetic and logic instructions affect the flag register. (B)</p> Signup and view all the answers

What is the effect of the TEST instruction in terms of its operation?

<p>It doesn’t change the destination nor Flag bits. (D)</p> Signup and view all the answers

Which statement correctly describes the NOT and NEG instructions?

<p>NOT is a logic instruction, but NEG is an arithmetic instruction. (A)</p> Signup and view all the answers

If the register AL contains the binary value 01010010B, what will AL contain after executing the NEG AL instruction?

<p>10101101 (B)</p> Signup and view all the answers

After executing AND DX, [SI] with given values DX = AAAAH, SI = 0100, what is the resulting value?

<p>A00AH (B)</p> Signup and view all the answers

What is the result in the destination operand after executing the instruction XOR AX, [SI+BX] given AX = 5555H and BX = 0010H?

<p>55AAH (D)</p> Signup and view all the answers

What is the value of the destination operand after executing NOT [0300H] if DS: 300H equals AAH?

<p>FCFFH (B)</p> Signup and view all the answers

What does the command SHR ECX, 10 signify?

<p>ECX is logically shifted right 10 places (A)</p> Signup and view all the answers

To perform an arithmetic left shift on the register BX five times, which instruction should be used?

<p>SAL BX, 5 (B)</p> Signup and view all the answers

What does the instruction RCL BL, 6 indicate?

<p>BL rotate left through carry 6 places (C)</p> Signup and view all the answers

Which instruction is used to rotate register AH to the right including the carry flag, using the number specified in CL?

<p>RCR AH, CL (C)</p> Signup and view all the answers

What does the instruction ROR EDX, 18 do?

<p>EDX rotate right 18 places (C)</p> Signup and view all the answers

What is the typical size of the opcode field in a machine language instruction?

<p>either 1 or 2 bytes long (D)</p> Signup and view all the answers

What does a mode field value of 11 indicate?

<p>16-bit signed displacement (B)</p> Signup and view all the answers

What does a mode field value of 00 signify?

<p>No displacement (D)</p> Signup and view all the answers

What is indicated by a mode field value of 10?

<p>8-bit signed extended displacement (C)</p> Signup and view all the answers

Given the machine language instruction 8A15H, what is the corresponding assembly language instruction?

<p>MOV DL, [DI] (B)</p> Signup and view all the answers

For the machine language instruction 8BECH, what is the corresponding assembly language instruction?

<p>MOV SP, BP (A)</p> Signup and view all the answers

What is the machine language instruction for the assembly language instruction Mov SI, [BX+2]?

<p>8B7702H (C)</p> Signup and view all the answers

What is the address accessed by MOV [SI+100H], EAX with DS=1000H, SS=2000H, BP=1500H, BX=0100, and SI=0200H?

<p>10400H (D)</p> Signup and view all the answers

What is the corresponding assembly language instruction for the machine language instruction 8A5501H?

<p>MOV DL, [DI] (D)</p> Signup and view all the answers

The bit that is set if the result of the computation or comparison performed by an instruction is zero is known as what?

<p>Zero flag (ZF) (A)</p> Signup and view all the answers

Which bit is set when the result of any computation is negative?

<p>Sign flag (SF) (D)</p> Signup and view all the answers

In real mode, if the segment register value is E001H, what is the starting address of the segment?

<p>E001H (A)</p> Signup and view all the answers

In real mode, if the segment register value is 1234H, what is the ending address of the segment?

<p>12340H (C)</p> Signup and view all the answers

What is the value of the physical address of the combination B2C0 : FA12 in real mode?

<p>1ACD2H (B)</p> Signup and view all the answers

What describes the memory segment's location, length, and access rights?

<p>Descriptor (B)</p> Signup and view all the answers

What is the maximum length of the local and global descriptor tables?

<p>64KB (C)</p> Signup and view all the answers

In the descriptor format of the 80286 microprocessor, how many bytes does the base address consist of?

<p>4 bytes (C)</p> Signup and view all the answers

Flashcards

MOV AX, 123AH instruction

Moves the hexadecimal value 123AH into the AX register.

Instruction to copy DS into AX

MOV AX, DS copies the contents of the Data Segment register (DS) into the AX register.

Stack Memory Access

LIFO (Last-In, First-Out) memory organization where items are added and removed from the top.

PUSH AX instruction

Pushes the contents of the AX register onto the stack.

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POP Instruction

Removes and stores at the particular register from the stack.

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BP register Usage

When BP addresses data, it refers to the Stack Segment (SS).

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BX register Usage

When BX addresses data, it most often refers to the Data Segment (DS).

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IP register's Usage

When IP addresses memory, it refers to the Code Segment (CS) which contains the instructions.

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SUB [DI], AX

Subtracts the value in the AX register from the word-sized memory location addressed by DI (within the data segment).

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SUB AX, BX

Subtracts the value in the BX register from the value in the AX register, storing the result in AX.

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IMUL instruction

Performs signed multiplication.

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Multiplication of two 8-bit numbers

Results in a 16-bit product.

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Multiplication of two 16-bit numbers

Results in a 32-bit product.

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MUL CL

Multiplies the value in the AL register by the value in the CL register, storing the unsigned product in the AX register.

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IMUL CX

Multiplies the value in the AX register by the value in the CX register, storing the signed product in the DX:AX registers.

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Signed Division Instruction

The IDIV instruction performs signed integer division, dividing the 32-bit dividend (DX:AX) by a byte or word operand. The quotient is stored in AX (or AL for byte division) and the remainder in DX (or AH for byte division).

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Unsigned Division Instruction

The DIV instruction performs unsigned integer division, dividing the 32-bit dividend (DX:AX) by a byte or word operand. The quotient is stored in AX (or AL for byte division) and the remainder in DX (or AH for byte division).

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Accessing Stack Segment Memory

When dividing with DIV or IDIV, you can access the operand from the stack segment memory using [BP]. This allows you to operate on data stored on the stack.

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What affects the Flag Register?

Arithmetic and logic instructions, such as addition, subtraction, AND, OR, etc., affect the flags in the flag register. The flags indicate the result of the operation (carry, parity, zero, sign etc.).

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The TEST instruction

The TEST instruction performs a bitwise AND operation between the destination operand and the source operand. It sets the flags based on the result, but doesn't modify the destination operand.

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What are NOT and NEG?

Both NOT and NEG are arithmetic instructions: NOT performs a bitwise complement (inverting all bits), while NEG computes the two's complement of the operand, meaning its arithmetic negation.

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Bit Manipulating Instructions

Instructions like AND, OR, and XOR are used to manipulate individual bits within registers or memory. This enables you to selectively modify specific bits based on their logical combination.

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Combining Data with OR

The OR instruction performs a bitwise OR operation between the destination and source operands. Sets bits in the destination operand if either corresponding bits in the destination or source are set.

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Mode Field: 11

The mode field value of '11' indicates the use of register-addressing mode.

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Mode Field: 00

A mode field value of '00' implies no displacement is used, meaning the address is directly accessed.

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Mode Field: 10

A mode field value of '10' signifies an 8-bit signed extended displacement, which is added to the base address.

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Mode Field: 01

A mode field value of '01' denotes a 16-bit signed displacement, which is added to the base address.

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Machine Language: 8A15H

The machine language instruction '8A15H' translates to the assembly language instruction MOV [DI], DL.

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Machine Language: 8BECH

The machine language instruction '8BECH' translates to the assembly language instruction MOV BP, SP.

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Assembly Language: MOV SI, [BX+2]

The assembly instruction 'MOV SI, [BX+2]' moves the value stored at the memory location addressed by BX+2 into the SI register.

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Assembly Language: MOV [BX+4], DI

The assembly instruction 'MOV [BX+4], DI' copies the value from the DI register into the memory location addressed by BX+4.

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Zero Flag (ZF)

The Zero Flag (ZF) is a status flag in a CPU that is set to 1 if the result of an arithmetic or logical operation is zero, otherwise it is reset to 0.

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Sign Flag (SF)

The Sign Flag (SF) is a status flag that reflects the sign bit of the result of an arithmetic or logical operation. If the most significant (leftmost) bit of the result is 1, indicating a negative number, SF is set to 1. Otherwise, SF is 0.

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Real Mode Addressing

In real mode, memory is addressed using a segment and offset. The physical address is calculated by multiplying the segment value by 16 and adding the offset value.

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Segment Register

Segment registers (CS, DS, SS, ES) hold the starting address of a memory segment, which is then used to calculate the actual physical address of data within the segment.

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Descriptor

A descriptor is a data structure that holds information about a memory segment, including its location, length, and access rights.

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Protected Mode

Protected mode is an operational mode of a CPU that provides more sophisticated memory management and security features, giving the operating system greater control over memory access.

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Local Descriptor Table (LDT)

A Local Descriptor Table (LDT) is a table that contains descriptors specific to a particular process or task, providing access to the memory space dedicated to that process.

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Global Descriptor Table (GDT)

The Global Descriptor Table (GDT) is a system-wide table that contains descriptors for memory segments that are shared across different tasks or processes.

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XOR AX, [SI+BX]

Performs a bitwise exclusive OR operation between the value in the AX register and the value at the memory location calculated by adding the contents of the SI and BX registers. The result is stored in the AX register.

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NOT [0300H]

Performs a bitwise NOT operation on the byte stored at the memory location 0300H. This effectively inverts all the bits of the byte.

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SHR ECX, 10

This instruction performs a logical right shift on the ECX register by 10 bits. In a logical right shift, zeros are shifted in from the left side, potentially losing data on the right side.

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SAL BX, 5

This instruction performs an arithmetic left shift on the BX register by 5 bits. In an arithmetic left shift, the most significant bit (MSB) is copied to the leftmost position. The least significant bit (LSB) is filled with a 0.

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RCL BL, 6

This instruction performs a rotate left through carry operation on the BL register by 6 bits. In a rotate operation, the bits are shifted circularly (shifted bits re-enter the register from the other side). The carry flag is involved as the MSB goes to the carry flag and the carry flag goes to the LSB.

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RCR AH, CL

This instruction performs a rotate right through carry operation on the AH register by the number of bits specified in the CL register.

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ROR EDX, 18

This instruction performs a rotate right on the EDX register by 18 bits. Bits shifted out of the register are re-inserted from the other side.

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Opcode Field

The opcode field of a machine language instruction determines the operation to be performed. In many architectures, it consists of one or two bytes encoding the specific action the processor will take.

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Study Notes

Microprocessor Question Bank

  • Memory Above 1MB: Called extended memory
  • First 1MB of Memory: Often called real memory
  • Cache Memory: High-speed temporary storage for data transfer between memory and the CPU
  • 8KB Cache Microprocessor: Intel 80486
  • 16MB Memory System Microprocessor: Intel 80386
  • Address Bus: Requests memory or I/O location from memory or I/O devices
  • Data Bus: Transfers information between the microprocessor, memory, and I/O addresses
  • Control Bus Lines: Select and cause memory or I/O to perform read or write operations
  • IORC Signal: Purpose is memory write control
  • IOWC Signal: Purpose is I/O write control
  • MWTC Signal: Purpose is memory write control
  • MRDC Signal: A. Purpose is memory read control
  • Bus: Set of common connections that carries the same type of information
  • Memory Map: Windows & DOS memory have different memory maps
  • Memory Size and Bus Width: Memory size depends on the address bus width. If data = 16-bit and address = 26-bit in 80386EX, memory size is 64MB. If data = 16-bit and address = 20-bit in 8086, memory size is 1MB.
  • Pentium Microprocessor and Address/Memory Size: 32-bit address bus = 4GB memory on Pentium and 4GB on Pentium 4
  • TPA in Memory Map (Windows): 2GB
  • System Area in Windows Memory Map: 640KB
  • TPA in DOS Memory Map (DOS): 640KB
  • System Area in DOS Memory Map (DOS): 384KB
  • Microprocessor Function: Data transfer between itself and memory, program flow with decisions, simple arithmetic & logic operations
  • BIU (Bus Interface Unit): Fetches instructions, reads data from memory and I/O ports, writes data to memory and I/O ports.
  • EU (Execution Unit): Executes instructions.
  • Code Segment Register in 8086: Consists of 16 bits
  • Stack Segment Register in 8086: Consists of 16 bits
  • 8086 Microprocessor: 16-bit microprocessor, 20-bit address bus, 1MB memory
  • Maximum Segment Size in 8086: 64KB
  • Code Segment Register (CS): Contains the base or start address of the current code segment
  • Data Segment Register (DS): Contains the 16-bit address pointing to the next instruction code within 64KB
  • Instruction Pointer (IP): Contains the 16-bit offset address used with data segment area
  • Base Pointer (BP): Points to the current data segment .
  • Stack Pointer (SP): Points to the current stack
  • Register, AX: Consist of 16 bit
  • Register, BL: Consist of 8 bit
  • Flags Register: Responsible for indicating the result of addition, memory condition, or condition of result of ALU operations or result of subtraction
  • Output Flag: If the results of computation is zero
  • Carry Flag: If there is a carry in case of addition
  • Overflow Flag: If the result of a computation is negative
  • Memory Addresses: Real-mode addressing in 8086, involves segment and offset values

Other Information

  • Descriptor Tables: Maximum length is 64KB, base addresses(3-bytes), limits(2.5 bytes) vary with microprocessor type (80286, 80386, Pentium II).
  • Instruction Types: Register addressing mode, direct addressing mode, immediate addressing mode, based indexed addressing mode.
  • Flags (Flags Register): Zero flag, carry flag, sign flag, overflow flag
  • Arithmetic Operations: instructions involving addition, subtraction, multiplication, division.
  • Logical Operations: Instructions like AND, OR, XOR, NOT
  • Shift operations: instructions involve shifting right/left
  • Transfer Instructions: instructions for transfer data between registers, transfer data between register and memory.

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