8086 Microprocessor Architecture

8086 Microprocessor Architecture

Overview

• The 8086 microprocessor is a 16-bit microprocessor introduced by Intel in 1979
• It is a member of the x86 family of microprocessors
• The 8086 is a significant improvement over its predecessors, with a larger address space and improved performance

Architecture

• Bus Structure:
  • 16-bit data bus
  • 20-bit address bus (allowing for 1MB of address space)
• Registers:
  • 14 registers in total
  • 8 general-purpose registers (AX, BX, CX, DX, SI, DI, BP, SP)
  • 6 segment registers (CS, DS, ES, FS, GS, SS)
• Fetch-Decode-Execute Cycle:
  1. Instruction Fetch: The CPU retrieves an instruction from memory
  2. Instruction Decode: The CPU decodes the instruction and determines the operation to be performed
  3. Instruction Execute: The CPU executes the instruction

Execution Units

• Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations
• Barrel Shifter: Performs shift and rotate operations
• Multiplier/Divider: Performs multiplication and division operations

Memory Organization

• Segmentation: The 8086 uses a segmented memory architecture, dividing the 1MB address space into 16 segments of 64KB each
• Segment Registers: The segment registers (CS, DS, ES, FS, GS, SS) are used to specify the base address of each segment

Instruction Set

• Instruction Length: Instructions can be 1, 2, or 3 bytes long
• Instruction Format: Instructions consist of an opcode, followed by optional operands (registers, memory addresses, or immediates)
• Addressing Modes: The 8086 supports several addressing modes, including:
  • Register indirect
  • Memory direct
  • Register indirect with displacement
  • Base-plus-index

Control Unit

• Instruction Pointer (IP): The IP register points to the next instruction to be fetched
• Flags: The 8086 has 9 flags that are used to indicate the result of arithmetic and logical operations
• Interrupt Handling: The 8086 has a built-in interrupt system, allowing for efficient handling of interrupts and exceptions

8086 Microprocessor Architecture

Overview

• 16-bit microprocessor introduced by Intel in 1979
• Member of the x86 family of microprocessors
• Significant improvement over predecessors with larger address space and improved performance

Bus Structure

• 16-bit data bus
• 20-bit address bus, allowing for 1MB of address space

Registers

• 14 registers in total
• 8 general-purpose registers: AX, BX, CX, DX, SI, DI, BP, SP
• 6 segment registers: CS, DS, ES, FS, GS, SS

Fetch-Decode-Execute Cycle

• Instruction Fetch: CPU retrieves an instruction from memory
• Instruction Decode: CPU decodes the instruction and determines the operation to be performed
• Instruction Execute: CPU executes the instruction

Execution Units

• Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations
• Barrel Shifter: Performs shift and rotate operations
• Multiplier/Divider: Performs multiplication and division operations

Memory Organization

• Segmented memory architecture, dividing the 1MB address space into 16 segments of 64KB each
• Segment registers specify the base address of each segment

Instruction Set

• Instructions can be 1, 2, or 3 bytes long
• Instruction format: opcode, followed by optional operands (registers, memory addresses, or immediates)
• Addressing modes: register indirect, memory direct, register indirect with displacement, base-plus-index

Control Unit

• Instruction Pointer (IP): points to the next instruction to be fetched
• 9 flags: indicate the result of arithmetic and logical operations
• Built-in interrupt system: allows for efficient handling of interrupts and exceptions

Overview

• 8086 microprocessor is a 16-bit microprocessor introduced by Intel in 1979
• It is a significant improvement over its predecessor, the 8080, with enhanced performance and functionality

Architecture

Bus Structure

• 16-bit address bus and a 16-bit data bus
• Address bus is divided into two parts: A0-A7 (lower byte) and A8-A15 (upper byte)
• Data bus is divided into two parts: D0-D7 (lower byte) and D8-D15 (upper byte)

Registers

General-Purpose Registers

• 14 registers, each 16 bits wide
• AX, BX, CX, DX (accumulator, base, counter, and data registers)
• SI, DI (source and destination index registers)
• BP, SP (base and stack pointers)
• IX (index register)

Segment Registers

• 4 segment registers, each 16 bits wide
• CS (code segment)
• DS (data segment)
• ES (extra segment)
• SS (stack segment)

Execution

Instruction Cycle

• Fetch: retrieve an instruction from memory
• Decode: decode the instruction
• Operate: execute the instruction
• Store: store the results

Pipelining

• 6-stage pipeline:
• Instruction Fetch
• Instruction Decode
• Operand Fetch
• Execution
• Memory Access
• Write Back

Memory Organization

Segmentation

• Segmented memory organization
• Code segment (CS)
• Data segment (DS)
• Extra segment (ES)
• Stack segment (SS)
• Each segment can have a maximum size of 64 KB

Memory Addressing

• Real-mode addressing
• 20-bit address space (2^20 = 1,048,576 bytes)
• 16-bit segment registers and 16-bit offset registers

Other Features

Interrupt Handling

• Single interrupt request pin (INT) and a single interrupt acknowledge pin (INTA)
• Supports 256 interrupt vectors

Clock Speed

• Original 8086 has a clock speed of 5 MHz
• Later versions of the 8086, such as the 8086-2, have higher clock speeds (up to 8 MHz)